mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 00:48:52 +09:00
![Stefan Roese](/assets/img/avatar_default.png)
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
498 lines
12 KiB
C
498 lines
12 KiB
C
/*
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* (C) Copyright 2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc440.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/4xx_pcie.h>
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#include <asm/gpio.h>
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#include <asm/errno.h>
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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DECLARE_GLOBAL_DATA_PTR;
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#define CONFIG_SYS_BCSR3_PCIE 0x10
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#define BOARD_CANYONLANDS_PCIE 1
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#define BOARD_CANYONLANDS_SATA 2
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#define BOARD_GLACIER 3
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#define BOARD_ARCHES 4
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/*
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* Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
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* board specific values.
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*/
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#if defined(CONFIG_ARCHES)
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u32 ddr_wrdtr(u32 default_val) {
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return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
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}
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#else
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u32 ddr_wrdtr(u32 default_val) {
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return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
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}
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u32 ddr_clktr(u32 default_val) {
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return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
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}
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#endif
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#if defined(CONFIG_ARCHES)
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/*
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* FPGA read/write helper macros
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*/
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static inline int board_fpga_read(int offset)
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{
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int data;
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data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
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return data;
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}
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static inline void board_fpga_write(int offset, int data)
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{
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out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
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}
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/*
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* CPLD read/write helper macros
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*/
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static inline int board_cpld_read(int offset)
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{
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int data;
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out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
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data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
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return data;
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}
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static inline void board_cpld_write(int offset, int data)
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{
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out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
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out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
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}
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#else
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static int pvr_460ex(void)
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{
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u32 pvr = get_pvr();
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if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
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(pvr == PVR_460EX_RB))
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return 1;
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return 0;
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}
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#endif /* defined(CONFIG_ARCHES) */
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int board_early_init_f(void)
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{
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#if !defined(CONFIG_ARCHES)
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u32 sdr0_cust0;
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#endif
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC2ER, 0x00000000); /* disable all */
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */
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mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC3SR, 0xffffffff); /* clear all */
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mtdcr(UIC3ER, 0x00000000); /* disable all */
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mtdcr(UIC3CR, 0x00000000); /* all non-critical */
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mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC3SR, 0xffffffff); /* clear all */
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#if !defined(CONFIG_ARCHES)
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/* SDR Setting - enable NDFC */
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mfsdr(SDR0_CUST0, sdr0_cust0);
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sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
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SDR0_CUST0_NDFC_ENABLE |
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SDR0_CUST0_NDFC_BW_8_BIT |
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SDR0_CUST0_NDFC_ARE_MASK |
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SDR0_CUST0_NDFC_BAC_ENCODE(3) |
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(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
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mtsdr(SDR0_CUST0, sdr0_cust0);
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#endif
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/*
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* Configure PFC (Pin Function Control) registers
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* UART0: 4 pins
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*/
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mtsdr(SDR0_PFC1, 0x00040000);
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/* Enable PCI host functionality in SDR0_PCI0 */
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mtsdr(SDR0_PCI0, 0xe0000000);
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#if !defined(CONFIG_ARCHES)
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/* Enable ethernet and take out of reset */
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out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
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/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
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out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
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/* Enable USB host & USB-OTG */
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out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
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mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
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/* Setup PLB4-AHB bridge based on the system address map */
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mtdcr(AHB_TOP, 0x8000004B);
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mtdcr(AHB_BOT, 0x8000004B);
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if (pvr_460ex()) {
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/*
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* Configure USB-STP pins as alternate and not GPIO
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* It seems to be neccessary to configure the STP pins as GPIO
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* input at powerup (perhaps while USB reset is asserted). So
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* we configure those pins to their "real" function now.
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*/
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gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
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gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
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}
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#endif
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return 0;
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}
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#if !defined(CONFIG_ARCHES)
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static void canyonlands_sata_init(int board_type)
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{
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u32 reg;
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if (board_type == BOARD_CANYONLANDS_SATA) {
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/* Put SATA in reset */
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SDR_WRITE(SDR0_SRST1, 0x00020001);
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/* Set the phy for SATA, not PCI-E port 0 */
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reg = SDR_READ(PESDR0_PHY_CTL_RST);
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SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
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reg = SDR_READ(PESDR0_L0CLK);
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SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
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SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
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SDR_WRITE(PESDR0_L0DRV, 0x00000104);
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/* Bring SATA out of reset */
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SDR_WRITE(SDR0_SRST1, 0x00000000);
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}
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}
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#endif /* !defined(CONFIG_ARCHES) */
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int get_cpu_num(void)
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{
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int cpu = NA_OR_UNKNOWN_CPU;
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#if defined(CONFIG_ARCHES)
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int cpu_num;
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cpu_num = board_fpga_read(0x3);
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/* sanity check; assume cpu numbering starts and increments from 0 */
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if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
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cpu = cpu_num;
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#endif
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return cpu;
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}
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#if !defined(CONFIG_ARCHES)
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int checkboard(void)
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{
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char *s = getenv("serial#");
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if (pvr_460ex()) {
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printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
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if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
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gd->board_type = BOARD_CANYONLANDS_PCIE;
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else
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gd->board_type = BOARD_CANYONLANDS_SATA;
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} else {
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printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
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gd->board_type = BOARD_GLACIER;
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}
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switch (gd->board_type) {
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case BOARD_CANYONLANDS_PCIE:
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case BOARD_GLACIER:
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puts(", 2*PCIe");
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break;
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case BOARD_CANYONLANDS_SATA:
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puts(", 1*PCIe/1*SATA");
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break;
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}
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printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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canyonlands_sata_init(gd->board_type);
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return (0);
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}
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#else /* defined(CONFIG_ARCHES) */
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
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printf(" Revision %02x.%02x ",
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board_fpga_read(0x0), board_fpga_read(0x1));
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gd->board_type = BOARD_ARCHES;
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/* Only CPU0 has access to CPLD registers */
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if (get_cpu_num() == 0) {
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u8 cfg_sw = board_cpld_read(0x1);
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printf("(FPGA=%02x, CPLD=%02x)\n",
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board_fpga_read(0x2), board_cpld_read(0x0));
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printf(" Configuration Switch %d%d%d%d\n",
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((cfg_sw >> 3) & 0x01),
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((cfg_sw >> 2) & 0x01),
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((cfg_sw >> 1) & 0x01),
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((cfg_sw >> 0) & 0x01));
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} else
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printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
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if (s != NULL)
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printf(" Serial# %s\n", s);
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return 0;
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}
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#endif /* !defined(CONFIG_ARCHES) */
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#if defined(CONFIG_NAND_U_BOOT)
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/*
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* NAND booting U-Boot version uses a fixed initialization, since the whole
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* I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
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* code.
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*/
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phys_size_t initdram(int board_type)
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{
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return CONFIG_SYS_MBYTES_SDRAM << 20;
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}
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#endif
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#if defined(CONFIG_PCI)
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int board_pcie_first(void)
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{
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/*
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* Canyonlands with SATA enabled has only one PCIe slot
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* (2nd one).
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*/
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if (gd->board_type == BOARD_CANYONLANDS_SATA)
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return 1;
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return 0;
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}
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#endif /* CONFIG_PCI */
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int board_early_init_r (void)
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{
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/*
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* Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
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* boot EBC mapping only supports a maximum of 16MBytes
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* (4.ff00.0000 - 4.ffff.ffff).
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* To solve this problem, the FLASH has to get remapped to another
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* EBC address which accepts bigger regions:
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*
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* 0xfc00.0000 -> 4.cc00.0000
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*/
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/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
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#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
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#else
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mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
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#endif
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/* Remove TLB entry of boot EBC mapping */
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remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
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/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
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program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
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TLB_WORD2_I_ENABLE);
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/*
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* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
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* 0xfc00.0000 is possible
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*/
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/*
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* Clear potential errors resulting from auto-calibration.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return 0;
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}
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#if !defined(CONFIG_ARCHES)
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int misc_init_r(void)
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{
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u32 sdr0_srst1 = 0;
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u32 eth_cfg;
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u8 val;
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/*
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* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
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* This is board specific, so let's do it here.
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*/
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mfsdr(SDR0_ETH_CFG, eth_cfg);
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/* disable SGMII mode */
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eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
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SDR0_ETH_CFG_SGMII1_ENABLE |
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SDR0_ETH_CFG_SGMII0_ENABLE);
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/* Set the for 2 RGMII mode */
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/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
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eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
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if (pvr_460ex())
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eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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else
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eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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mtsdr(SDR0_ETH_CFG, eth_cfg);
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/*
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* The AHB Bridge core is held in reset after power-on or reset
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* so enable it now
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*/
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mfsdr(SDR0_SRST1, sdr0_srst1);
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sdr0_srst1 &= ~SDR0_SRST1_AHB;
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mtsdr(SDR0_SRST1, sdr0_srst1);
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/*
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* RTC/M41T62:
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* Disable square wave output: Batterie will be drained
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* quickly, when this output is not disabled
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*/
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val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
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val &= ~0x40;
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i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
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return 0;
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}
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#else /* defined(CONFIG_ARCHES) */
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int misc_init_r(void)
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{
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u32 eth_cfg = 0;
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u32 eth_pll;
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u32 reg;
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/*
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* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
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* This is board specific, so let's do it here.
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*/
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/* enable SGMII mode */
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eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
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SDR0_ETH_CFG_SGMII1_ENABLE |
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SDR0_ETH_CFG_SGMII2_ENABLE);
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/* Set EMAC for MDIO */
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eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
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/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
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eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
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mtsdr(SDR0_ETH_CFG, eth_cfg);
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/* reset all SGMII interfaces */
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mfsdr(SDR0_SRST1, reg);
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reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
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mtsdr(SDR0_SRST1, reg);
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mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
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mtsdr(SDR0_SRST1, 0x00000000);
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do {
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mfsdr(SDR0_ETH_PLL, eth_pll);
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} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
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return 0;
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}
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#endif /* !defined(CONFIG_ARCHES) */
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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extern void __ft_board_setup(void *blob, bd_t *bd);
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void ft_board_setup(void *blob, bd_t *bd)
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{
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__ft_board_setup(blob, bd);
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if (gd->board_type == BOARD_CANYONLANDS_SATA) {
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/*
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* When SATA is selected we need to disable the first PCIe
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* node in the device tree, so that Linux doesn't initialize
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* it.
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*/
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fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
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"disabled", sizeof("disabled"), 1);
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}
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if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
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/*
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* When PCIe is selected we need to disable the SATA
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* node in the device tree, so that Linux doesn't initialize
|
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* it.
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*/
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fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
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"disabled", sizeof("disabled"), 1);
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}
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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