mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 11:59:46 +09:00
1d3b852e52
Subtracts CONFIG_OPTEE_TZDRAM_SIZE from the available DRAM size so that the OPTEE memory is not override during u-boot relocation. Note the OPTEE live in the end part of DRAM and OPTEE boot process will itself subtract the DRAM region it lives in from the memory map passed to Linux. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
340 lines
9.4 KiB
C
340 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 NXP Semiconductors
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/io.h>
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <usb.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../../freescale/common/pfuze.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
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PAD_CTL_DSE_3P3V_49OHM)
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#define LCD_SYNC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
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PAD_CTL_DSE_3P3V_196OHM)
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#ifdef CONFIG_SYS_I2C_MXC
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C4 for PMIC */
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static struct i2c_pads_info i2c_pad_info4 = {
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.scl = {
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.i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
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.gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
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.gp = IMX_GPIO_NR(6, 16),
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},
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.sda = {
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.i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
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.gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
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.gp = IMX_GPIO_NR(6, 17),
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},
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};
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#endif
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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/* Subtract the defined OPTEE runtime firmware length */
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#ifdef CONFIG_OPTEE_TZDRAM_SIZE
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gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
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#endif
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return 0;
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}
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#ifdef CONFIG_POWER
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#define I2C_PMIC 3
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int power_init_board(void)
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{
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struct pmic *p;
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int ret;
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unsigned int reg, rev_id;
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ret = power_pfuze3000_init(I2C_PMIC);
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if (ret)
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return ret;
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p = pmic_get("PFUZE3000");
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ret = pmic_probe(p);
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if (ret)
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return ret;
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pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
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pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
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printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
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/* disable Low Power Mode during standby mode */
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pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
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reg |= 0x1;
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pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
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/* SW1A/1B mode set to APS/APS */
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reg = 0x8;
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pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
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pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
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/* SW1A/1B standby voltage set to 1.025V */
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reg = 0xd;
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pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
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pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
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/* decrease SW1B normal voltage to 0.975V */
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pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
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reg &= ~0x1f;
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reg |= PFUZE3000_SW1AB_SETP(975);
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pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
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return 0;
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}
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#endif
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static iomux_v3_cfg_t const wdog_pads[] = {
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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart5_pads[] = {
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MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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#ifdef CONFIG_FEC_MXC
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
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MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11)
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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gpio_request(FEC1_RST_GPIO, "phy_rst");
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gpio_direction_output(FEC1_RST_GPIO, 0);
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udelay(500);
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gpio_set_value(FEC1_RST_GPIO, 1);
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}
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int board_eth_init(bd_t *bis)
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{
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setup_iomux_fec();
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return fecmxc_initialize_multi(bis, 0,
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CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
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}
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
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= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
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clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
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(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
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IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
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return set_clk_enet(ENET_125MHZ);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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unsigned short val;
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/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= 0xffe7;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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#ifdef CONFIG_SYS_I2C_MXC
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setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
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#endif
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return 0;
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}
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#ifdef CONFIG_VIDEO_MXS
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static iomux_v3_cfg_t const lcd_pads[] = {
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MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
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MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
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MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
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MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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void setup_lcd(void)
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{
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imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
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gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness");
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gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable");
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/* Set Brightness to high */
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gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
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/* Set LCD enable to high */
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gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
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}
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#endif
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_VIDEO_MXS
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setup_lcd();
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#endif
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#ifdef CONFIG_FEC_MXC
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setup_fec();
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#endif
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return 0;
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}
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int board_late_init(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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/*
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* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
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* since we use PMIC_PWRON to reset the board.
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*/
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clrsetbits_le16(&wdog->wcr, 0, 0x10);
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: i.MX7D PICOSOM\n");
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return 0;
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}
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static iomux_v3_cfg_t const usb_otg2_pads[] = {
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MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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int board_ehci_hcd_init(int port)
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{
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switch (port) {
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case 0:
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
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ARRAY_SIZE(usb_otg2_pads));
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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int board_usb_phy_mode(int port)
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{
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switch (port) {
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case 0:
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return USB_INIT_DEVICE;
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case 1:
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return USB_INIT_HOST;
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default:
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return -EINVAL;
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}
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return 0;
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}
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