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https://github.com/brain-hackers/u-boot-brain
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b1e6c4c3d4
Many boot image configuration files refer to the appropriate documentation file, but these references contain typos in the directory and file name. Fix them. Also fix reference to doc/README.SPL file. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
123 lines
3.4 KiB
INI
123 lines
3.4 KiB
INI
/*
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* Copyright (C) 2009 Pegatron Corporation
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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* Copyright (C) 2009-2012 Genesi USA, Inc.
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*
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* BASED ON: imx51evk
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*
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* (C) Copyright 2009
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* Stefano Babic DENX Software Engineering sbabic@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not write to the Free Software
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* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
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* MA 02110-1301 USA
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM spi
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* DDR bus IOMUX PAD settings */
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DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
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DATA 4 0x73fa850c 0x20c5 # SDODT1
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DATA 4 0x73fa8510 0x20c5 # SDODT0
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DATA 4 0x73fa8848 0x4 # DDR_A1
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DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
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DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
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DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
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DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
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DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
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DATA 4 0x73fa8820 0x0 # DDRPKS
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DATA 4 0x73fa84ac 0xe5 # SDWE
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DATA 4 0x73fa84b0 0xe5 # SDCKE0
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DATA 4 0x73fa84b4 0xe5 # SDCKE1
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DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
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DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
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/*
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* Setting DDR for micron
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* 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
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* CAS=3 BL=4
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*/
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/* ESDCTL_ESDCTL0 */
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DATA 4 0x83fd9000 0x82a20000
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/* ESDCTL_ESDCTL1 */
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DATA 4 0x83fd9008 0x82a20000
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/* ESDCTL_ESDMISC */
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DATA 4 0x83fd9010 0xcaaaf6d0
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/* ESDCTL_ESDCFG0 */
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DATA 4 0x83fd9004 0x333574aa
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/* ESDCTL_ESDCFG1 */
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DATA 4 0x83fd900c 0x333574aa
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/* Init DRAM on CS0 */
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/* ESDCTL_ESDSCR */
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DATA 4 0x83fd9014 0x04008008
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DATA 4 0x83fd9014 0x0000801a
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DATA 4 0x83fd9014 0x0000801b
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DATA 4 0x83fd9014 0x00448019
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DATA 4 0x83fd9014 0x07328018
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DATA 4 0x83fd9014 0x04008008
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DATA 4 0x83fd9014 0x00008010
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DATA 4 0x83fd9014 0x00008010
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DATA 4 0x83fd9014 0x06328018
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DATA 4 0x83fd9014 0x03808019
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DATA 4 0x83fd9014 0x00408019
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DATA 4 0x83fd9014 0x00008000
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/* Init DRAM on CS1 */
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DATA 4 0x83fd9014 0x0400800c
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DATA 4 0x83fd9014 0x0000801e
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DATA 4 0x83fd9014 0x0000801f
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DATA 4 0x83fd9014 0x0000801d
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DATA 4 0x83fd9014 0x0732801c
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DATA 4 0x83fd9014 0x0400800c
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DATA 4 0x83fd9014 0x00008014
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DATA 4 0x83fd9014 0x00008014
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DATA 4 0x83fd9014 0x0632801c
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DATA 4 0x83fd9014 0x0380801d
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DATA 4 0x83fd9014 0x0042801d
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DATA 4 0x83fd9014 0x00008004
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/* Write to CTL0 */
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DATA 4 0x83fd9000 0xb2a20000
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/* Write to CTL1 */
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DATA 4 0x83fd9008 0xb2a20000
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/* ESDMISC */
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DATA 4 0x83fd9010 0xcaaaf6d0
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/* ESDCTL_ESDCDLYGD */
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DATA 4 0x83fd9034 0x90000000
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DATA 4 0x83fd9014 0x00000000
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