mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-08 11:13:45 +09:00
![]() On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted and it is not able to reach the Linux prompt. Comparing the watchdog behaviour on a revB versus revC board: - On a mx6qsabresd revB: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: WDOG ... - On a mx6qsabresd revC: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR. Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and is also safe for all mx6 boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de> |
||
---|---|---|
.. | ||
arm720t | ||
arm920t | ||
arm925t | ||
arm926ejs | ||
arm946es | ||
arm1136 | ||
arm1176 | ||
arm_intcm | ||
armv7 | ||
ixp | ||
pxa | ||
s3c44b0 | ||
sa1100 | ||
tegra20-common | ||
tegra-common | ||
u-boot.lds |