mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 19:56:18 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
530 lines
14 KiB
C
530 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* From coreboot southbridge/intel/bd82x6x/lpc.c
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <rtc.h>
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#include <pci.h>
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#include <asm/intel_regs.h>
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#include <asm/interrupt.h>
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#include <asm/io.h>
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#include <asm/ioapic.h>
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#include <asm/lpc_common.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define NMI_OFF 0
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#define ENABLE_ACPI_MODE_IN_COREBOOT 0
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#define TEST_SMM_FLASH_LOCKDOWN 0
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static int pch_enable_apic(struct udevice *pch)
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{
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u32 reg32;
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int i;
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/* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
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dm_pci_write_config8(pch, ACPI_CNTL, 0x80);
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writel(0, IO_APIC_INDEX);
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writel(1 << 25, IO_APIC_DATA);
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/* affirm full set of redirection table entries ("write once") */
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writel(1, IO_APIC_INDEX);
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reg32 = readl(IO_APIC_DATA);
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writel(1, IO_APIC_INDEX);
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writel(reg32, IO_APIC_DATA);
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writel(0, IO_APIC_INDEX);
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reg32 = readl(IO_APIC_DATA);
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debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f);
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if (reg32 != (1 << 25)) {
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printf("APIC Error - cannot write to registers\n");
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return -EPERM;
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}
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debug("Dumping IOAPIC registers\n");
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for (i = 0; i < 3; i++) {
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writel(i, IO_APIC_INDEX);
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debug(" reg 0x%04x:", i);
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reg32 = readl(IO_APIC_DATA);
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debug(" 0x%08x\n", reg32);
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}
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/* Select Boot Configuration register. */
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writel(3, IO_APIC_INDEX);
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/* Use Processor System Bus to deliver interrupts. */
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writel(1, IO_APIC_DATA);
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return 0;
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}
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static void pch_enable_serial_irqs(struct udevice *pch)
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{
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u32 value;
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/* Set packet length and toggle silent mode bit for one frame. */
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value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
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#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
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dm_pci_write_config8(pch, SERIRQ_CNTL, value);
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#else
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dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6));
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#endif
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}
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static int pch_pirq_init(struct udevice *pch)
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{
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uint8_t route[8], *ptr;
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if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch),
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"intel,pirq-routing", route, sizeof(route)))
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return -EINVAL;
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ptr = route;
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dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++);
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/*
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* TODO(sjg@chromium.org): U-Boot does not set up the interrupts
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* here. It's unclear if it is needed
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*/
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return 0;
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}
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static int pch_gpi_routing(struct udevice *pch)
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{
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u8 route[16];
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u32 reg;
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int gpi;
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if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch),
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"intel,gpi-routing", route, sizeof(route)))
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return -EINVAL;
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for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
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reg |= route[gpi] << (gpi * 2);
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dm_pci_write_config32(pch, 0xb8, reg);
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return 0;
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}
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static int pch_power_options(struct udevice *pch)
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{
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(pch);
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u8 reg8;
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u16 reg16, pmbase;
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u32 reg32;
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const char *state;
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int pwr_on;
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int nmi_option;
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int ret;
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/*
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* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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* 1 == S5 Soft Off
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*
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* If the option is not existent (Laptops), use Kconfig setting.
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* TODO(sjg@chromium.org): Make this configurable
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*/
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pwr_on = MAINBOARD_POWER_ON;
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dm_pci_read_config16(pch, GEN_PMCON_3, ®16);
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reg16 &= 0xfffe;
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switch (pwr_on) {
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case MAINBOARD_POWER_OFF:
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reg16 |= 1;
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state = "off";
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break;
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case MAINBOARD_POWER_ON:
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reg16 &= ~1;
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state = "on";
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break;
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case MAINBOARD_POWER_KEEP:
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reg16 &= ~1;
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state = "state keep";
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break;
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default:
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state = "undefined";
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}
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reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
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reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
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reg16 &= ~(1 << 10);
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reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
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reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
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dm_pci_write_config16(pch, GEN_PMCON_3, reg16);
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debug("Set power %s after power failure.\n", state);
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/* Set up NMI on errors. */
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reg8 = inb(0x61);
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reg8 &= 0x0f; /* Higher Nibble must be 0 */
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reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
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reg8 |= (1 << 2); /* PCI SERR# Disable for now */
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outb(reg8, 0x61);
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reg8 = inb(0x70);
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/* TODO(sjg@chromium.org): Make this configurable */
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nmi_option = NMI_OFF;
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if (nmi_option) {
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debug("NMI sources enabled.\n");
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reg8 &= ~(1 << 7); /* Set NMI. */
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} else {
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debug("NMI sources disabled.\n");
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/* Can't mask NMI from PCI-E and NMI_NOW */
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reg8 |= (1 << 7);
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}
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outb(reg8, 0x70);
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/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
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dm_pci_read_config16(pch, GEN_PMCON_1, ®16);
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reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
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reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
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reg16 |= (3 << 0); /* Periodic SMI every 8s */
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#endif
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dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
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/* Set the board's GPI routing. */
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ret = pch_gpi_routing(pch);
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if (ret)
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return ret;
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dm_pci_read_config16(pch, 0x40, &pmbase);
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pmbase &= 0xfffe;
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writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0),
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(ulong)pmbase + GPE0_EN);
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writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0),
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(ulong)pmbase + ALT_GP_SMI_EN);
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/* Set up power management block and determine sleep mode */
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reg32 = inl(pmbase + 0x04); /* PM1_CNT */
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reg32 &= ~(7 << 10); /* SLP_TYP */
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reg32 |= (1 << 0); /* SCI_EN */
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outl(reg32, pmbase + 0x04);
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/* Clear magic status bits to prevent unexpected wake */
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setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
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clrbits_le32(RCB_REG(0x3f02), 0xf);
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return 0;
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}
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static void pch_rtc_init(struct udevice *pch)
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{
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int rtc_failed;
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u8 reg8;
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dm_pci_read_config8(pch, GEN_PMCON_3, ®8);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~RTC_BATTERY_DEAD;
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dm_pci_write_config8(pch, GEN_PMCON_3, reg8);
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}
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debug("rtc_failed = 0x%x\n", rtc_failed);
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/* TODO: Handle power failure */
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if (rtc_failed)
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printf("RTC power failed\n");
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}
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/* CougarPoint PCH Power Management init */
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static void cpt_pm_init(struct udevice *pch)
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{
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debug("CougarPoint PM init\n");
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dm_pci_write_config8(pch, 0xa9, 0x47);
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setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
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setbits_le32(RCB_REG(0x228c), 1 << 0);
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setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
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setbits_le32(RCB_REG(0x0900), 1 << 14);
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writel(0xc0388400, RCB_REG(0x2304));
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setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
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setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
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clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
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writel(0x050f0000, RCB_REG(0x3318));
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writel(0x04000000, RCB_REG(0x3324));
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setbits_le32(RCB_REG(0x3340), 0xfffff);
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setbits_le32(RCB_REG(0x3344), 1 << 1);
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writel(0x0001c000, RCB_REG(0x3360));
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writel(0x00061100, RCB_REG(0x3368));
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writel(0x7f8fdfff, RCB_REG(0x3378));
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writel(0x000003fc, RCB_REG(0x337c));
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writel(0x00001000, RCB_REG(0x3388));
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writel(0x0001c000, RCB_REG(0x3390));
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writel(0x00000800, RCB_REG(0x33a0));
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writel(0x00001000, RCB_REG(0x33b0));
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writel(0x00093900, RCB_REG(0x33c0));
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writel(0x24653002, RCB_REG(0x33cc));
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writel(0x062108fe, RCB_REG(0x33d0));
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clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
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writel(0x01010000, RCB_REG(0x3a28));
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writel(0x01010404, RCB_REG(0x3a2c));
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writel(0x01041041, RCB_REG(0x3a80));
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clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
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setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
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setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */
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writel(0x00000001, RCB_REG(0x3a6c));
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clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
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clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
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writel(0, RCB_REG(0x33c8));
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setbits_le32(RCB_REG(0x21b0), 0xf);
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}
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/* PantherPoint PCH Power Management init */
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static void ppt_pm_init(struct udevice *pch)
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{
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debug("PantherPoint PM init\n");
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dm_pci_write_config8(pch, 0xa9, 0x47);
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setbits_le32(RCB_REG(0x2238), 1 << 0);
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setbits_le32(RCB_REG(0x228c), 1 << 0);
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setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
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setbits_le16(RCB_REG(0x0900), 1 << 14);
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writel(0xc03b8400, RCB_REG(0x2304));
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setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
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setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
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clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);
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writel(0x054f0000, RCB_REG(0x3318));
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writel(0x04000000, RCB_REG(0x3324));
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setbits_le32(RCB_REG(0x3340), 0xfffff);
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setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));
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writel(0x0001c000, RCB_REG(0x3360));
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writel(0x00061100, RCB_REG(0x3368));
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writel(0x7f8fdfff, RCB_REG(0x3378));
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writel(0x000003fd, RCB_REG(0x337c));
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writel(0x00001000, RCB_REG(0x3388));
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writel(0x0001c000, RCB_REG(0x3390));
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writel(0x00000800, RCB_REG(0x33a0));
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writel(0x00001000, RCB_REG(0x33b0));
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writel(0x00093900, RCB_REG(0x33c0));
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writel(0x24653002, RCB_REG(0x33cc));
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writel(0x067388fe, RCB_REG(0x33d0));
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clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
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writel(0x01010000, RCB_REG(0x3a28));
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writel(0x01010404, RCB_REG(0x3a2c));
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writel(0x01040000, RCB_REG(0x3a80));
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clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
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/* SATA 2/3 disabled */
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setbits_le32(RCB_REG(0x3a84), 1 << 24);
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/* SATA 4/5 disabled */
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setbits_le32(RCB_REG(0x3a88), 1 << 0);
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writel(0x00000001, RCB_REG(0x3a6c));
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clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);
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clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
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setbits_le32(RCB_REG(0x33a4), (1 << 0));
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writel(0, RCB_REG(0x33c8));
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setbits_le32(RCB_REG(0x21b0), 0xf);
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}
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static void enable_hpet(void)
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{
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/* Move HPET to default address 0xfed00000 and enable it */
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clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
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}
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static void enable_clock_gating(struct udevice *pch)
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{
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u32 reg32;
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u16 reg16;
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setbits_le32(RCB_REG(0x2234), 0xf);
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dm_pci_read_config16(pch, GEN_PMCON_1, ®16);
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reg16 |= (1 << 2) | (1 << 11);
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dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
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pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31);
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pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7);
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pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31);
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pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7);
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reg32 = readl(RCB_REG(CG));
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reg32 |= (1 << 31);
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reg32 |= (1 << 29) | (1 << 28);
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reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
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reg32 |= (1 << 16);
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reg32 |= (1 << 17);
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reg32 |= (1 << 18);
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reg32 |= (1 << 22);
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reg32 |= (1 << 23);
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reg32 &= ~(1 << 20);
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reg32 |= (1 << 19);
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reg32 |= (1 << 0);
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reg32 |= (0xf << 1);
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writel(reg32, RCB_REG(CG));
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setbits_le32(RCB_REG(0x38c0), 0x7);
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setbits_le32(RCB_REG(0x36d4), 0x6680c004);
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setbits_le32(RCB_REG(0x3564), 0x3);
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}
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static void pch_disable_smm_only_flashing(struct udevice *pch)
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{
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u8 reg8;
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debug("Enabling BIOS updates outside of SMM... ");
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dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */
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reg8 &= ~(1 << 5);
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dm_pci_write_config8(pch, 0xdc, reg8);
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}
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static void pch_fixups(struct udevice *pch)
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{
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u8 gen_pmcon_2;
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/* Indicate DRAM init done for MRC S3 to know it can resume */
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dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2);
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gen_pmcon_2 |= (1 << 7);
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dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2);
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/* Enable DMI ASPM in the PCH */
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clrbits_le32(RCB_REG(0x2304), 1 << 10);
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setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
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setbits_le32(RCB_REG(0x21a8), 0x3);
|
|
}
|
|
|
|
static void set_spi_speed(void)
|
|
{
|
|
u32 fdod;
|
|
|
|
/* Observe SPI Descriptor Component Section 0 */
|
|
writel(0x1000, RCB_REG(SPI_DESC_COMP0));
|
|
|
|
/* Extract the1 Write/Erase SPI Frequency from descriptor */
|
|
fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
|
|
fdod >>= 24;
|
|
fdod &= 7;
|
|
|
|
/* Set Software Sequence frequency to match */
|
|
clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
|
|
}
|
|
|
|
static int lpc_init_extra(struct udevice *dev)
|
|
{
|
|
struct udevice *pch = dev->parent;
|
|
|
|
debug("pch: lpc_init\n");
|
|
dm_pci_write_bar32(pch, 0, 0);
|
|
dm_pci_write_bar32(pch, 1, 0xff800000);
|
|
dm_pci_write_bar32(pch, 2, 0xfec00000);
|
|
dm_pci_write_bar32(pch, 3, 0x800);
|
|
dm_pci_write_bar32(pch, 4, 0x900);
|
|
|
|
/* Set the value for PCI command register. */
|
|
dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);
|
|
|
|
/* IO APIC initialization. */
|
|
pch_enable_apic(pch);
|
|
|
|
pch_enable_serial_irqs(pch);
|
|
|
|
/* Setup the PIRQ. */
|
|
pch_pirq_init(pch);
|
|
|
|
/* Setup power options. */
|
|
pch_power_options(pch);
|
|
|
|
/* Initialize power management */
|
|
switch (pch_silicon_type(pch)) {
|
|
case PCH_TYPE_CPT: /* CougarPoint */
|
|
cpt_pm_init(pch);
|
|
break;
|
|
case PCH_TYPE_PPT: /* PantherPoint */
|
|
ppt_pm_init(pch);
|
|
break;
|
|
default:
|
|
printf("Unknown Chipset: %s\n", pch->name);
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/* Initialize the real time clock. */
|
|
pch_rtc_init(pch);
|
|
|
|
/* Initialize the High Precision Event Timers, if present. */
|
|
enable_hpet();
|
|
|
|
/* Initialize Clock Gating */
|
|
enable_clock_gating(pch);
|
|
|
|
pch_disable_smm_only_flashing(pch);
|
|
|
|
pch_fixups(pch);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bd82x6x_lpc_early_init(struct udevice *dev)
|
|
{
|
|
set_spi_speed();
|
|
|
|
/* Setting up Southbridge. In the northbridge code. */
|
|
debug("Setting up static southbridge registers\n");
|
|
dm_pci_write_config32(dev->parent, PCH_RCBA_BASE,
|
|
RCB_BASE_ADDRESS | 1);
|
|
dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
|
|
|
|
/* Enable ACPI BAR */
|
|
dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80);
|
|
|
|
debug("Disabling watchdog reboot\n");
|
|
setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
|
|
outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
|
|
|
|
dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1);
|
|
dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bd82x6x_lpc_probe(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
|
|
if (!(gd->flags & GD_FLG_RELOC)) {
|
|
ret = lpc_common_early_init(dev);
|
|
if (ret) {
|
|
debug("%s: lpc_early_init() failed\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
return bd82x6x_lpc_early_init(dev);
|
|
}
|
|
|
|
return lpc_init_extra(dev);
|
|
}
|
|
|
|
static const struct udevice_id bd82x6x_lpc_ids[] = {
|
|
{ .compatible = "intel,bd82x6x-lpc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
|
|
.name = "lpc",
|
|
.id = UCLASS_LPC,
|
|
.of_match = bd82x6x_lpc_ids,
|
|
.probe = bd82x6x_lpc_probe,
|
|
};
|