mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
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*/
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#ifndef _BAYTRAIL_IOMAP_H_
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#define _BAYTRAIL_IOMAP_H_
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/* Memory Mapped IO bases */
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/* PCI Configuration Space */
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#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
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#define MCFG_BASE_SIZE 0x10000000
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/* Temporary Base Address */
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#define TEMP_BASE_ADDRESS 0xfd000000
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/* Transactions in this range will abort */
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#define ABORT_BASE_ADDRESS 0xfeb00000
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#define ABORT_BASE_SIZE 0x00100000
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/* High Performance Event Timer */
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#define HPET_BASE_ADDRESS 0xfed00000
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#define HPET_BASE_SIZE 0x400
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/* SPI Bus */
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#define SPI_BASE_ADDRESS 0xfed01000
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#define SPI_BASE_SIZE 0x400
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/* Power Management Controller */
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#define PMC_BASE_ADDRESS 0xfed03000
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#define PMC_BASE_SIZE 0x400
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#define GEN_PMCON1 0x20
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#define UART_EN (1 << 24)
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#define DISB (1 << 23)
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#define MEM_SR (1 << 21)
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#define SRS (1 << 20)
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#define CTS (1 << 19)
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#define MS4V (1 << 18)
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#define PWR_FLR (1 << 16)
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#define PME_B0_S5_DIS (1 << 15)
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#define SUS_PWR_FLR (1 << 14)
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#define WOL_EN_OVRD (1 << 13)
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#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
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#define GEN_RST_STS (1 << 9)
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#define RPS (1 << 2)
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#define AFTERG3_EN (1 << 0)
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#define GEN_PMCON2 0x24
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#define SLPSX_STR_POL_LOCK (1 << 18)
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#define BIOS_PCI_EXP_EN (1 << 10)
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#define PWRBTN_LVL (1 << 9)
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#define SMI_LOCK (1 << 4)
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/* Power Management Unit */
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#define PUNIT_BASE_ADDRESS 0xfed05000
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#define PUNIT_BASE_SIZE 0x800
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/* Intel Legacy Block */
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#define ILB_BASE_ADDRESS 0xfed08000
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#define ILB_BASE_SIZE 0x400
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/* IO Memory */
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#define IO_BASE_ADDRESS 0xfed0c000
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#define IO_BASE_OFFSET_GPSCORE 0x0000
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#define IO_BASE_OFFSET_GPNCORE 0x1000
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#define IO_BASE_OFFSET_GPSSUS 0x2000
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#define IO_BASE_SIZE 0x4000
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/* Root Complex Base Address */
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#define RCBA_BASE_ADDRESS 0xfed1c000
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#define RCBA_BASE_SIZE 0x400
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/* MODPHY */
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#define MPHY_BASE_ADDRESS 0xfef00000
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#define MPHY_BASE_SIZE 0x100000
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/* IO Port bases */
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#define ACPI_BASE_ADDRESS 0x0400
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#define ACPI_BASE_SIZE 0x80
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#define PM1_STS 0x00
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#define PM1_CNT 0x04
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#define GPIO_BASE_ADDRESS 0x0500
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#define GPIO_BASE_SIZE 0x100
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#define SMBUS_BASE_ADDRESS 0xefa0
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#endif /* _BAYTRAIL_IOMAP_H_ */
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