85 lines
1.8 KiB
C
85 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/imx8mq_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
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static iomux_v3_cfg_t const wdog_pads[] = {
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IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart_pads[] = {
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IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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return 0;
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}
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Use 125M anatop REF_CLK1 for ENET1, not from external */
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clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
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return set_clk_enet(ENET_125MHZ);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_init(void)
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{
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setup_fec();
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return 0;
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
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env_set("board_name", "imx8mq-cm");
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env_set("board_rev", "v2.0");
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}
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return 0;
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}
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