mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-28 13:53:44 +09:00
765547dc5e
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
330 lines
8.7 KiB
C
330 lines
8.7 KiB
C
/*
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* Copyright 2009 Freescale Semiconductor.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include <ioports.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include "bcsr.h"
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phys_size_t fixed_sdram(void);
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* QE_MUX_MDC */
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{2, 31, 1, 0, 1}, /* QE_MUX_MDC */
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/* QE_MUX_MDIO */
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{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
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/* UCC_1_RGMII */
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{2, 11, 2, 0, 1}, /* CLK12 */
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{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
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{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
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{0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
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{0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
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{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
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{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
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{0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
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{0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
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{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
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{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
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{2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
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{2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
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/* UCC_2_RGMII */
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{2, 16, 2, 0, 3}, /* CLK17 */
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{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
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{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
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{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
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{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
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{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
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{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
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{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
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{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
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{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
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{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
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{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
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{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
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{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
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};
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void local_bus_init(void);
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int board_early_init_f (void)
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{
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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enable_8569mds_flash_write();
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#ifdef CONFIG_QE
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enable_8569mds_qe_mdio();
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#endif
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#if CONFIG_SYS_I2C2_OFFSET
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/* Enable I2C2 signals instead of SD signals */
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volatile struct ccsr_gur *gur;
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gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
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gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
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gur->plppar1 |= PLPPAR1_I2C2_VAL;
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gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
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gur->plpdir1 |= PLPDIR1_I2C2_VAL;
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disable_8569mds_brd_eeprom_write_protect();
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#endif
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return 0;
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}
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int checkboard (void)
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{
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printf ("Board: 8569 MDS\n");
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_DDR_DLL)
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/*
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* Work around to stabilize DDR DLL MSYNC_IN.
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* Errata DDR9 seems to have been fixed.
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* This is now the workaround for Errata DDR11:
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* Override DLL = 1, Course Adj = 1, Tap Select = 0
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*/
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volatile ccsr_gur_t *gur =
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(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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out_be32(&gur->ddrdllcr, 0x81000000);
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udelay(200);
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#endif
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#ifdef CONFIG_SPD_EEPROM
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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phys_size_t fixed_sdram(void)
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{
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volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
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uint d_init;
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out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
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out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
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out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
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out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
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out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
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out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
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#if defined (CONFIG_DDR_ECC)
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out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
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out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
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out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
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#endif
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udelay(500);
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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d_init = 1;
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debug("DDR - 1st controller: memory initializing\n");
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/*
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* Poll until memory is initialized.
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* 512 Meg at 400 might hit this 200 times or so.
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*/
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
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udelay(1000);
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}
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debug("DDR: memory initialized\n\n");
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udelay(500);
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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out_be32(&gur->lbiuiplldcr1, 0x00078080);
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if (clkdiv == 16)
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out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
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else if (clkdiv == 8)
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out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
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else if (clkdiv == 4)
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out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
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out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
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}
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif /* CONFIG_PCIE1 */
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extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
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extern void fsl_pci_init(struct pci_controller *hose);
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int first_free_busno = 0;
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#ifdef CONFIG_PCI
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void
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pci_init_board(void)
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{
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volatile ccsr_gur_t *gur;
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uint io_sel;
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uint host_agent;
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gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci;
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struct pci_controller *hose;
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int pcie_ep;
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struct pci_region *r;
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int pcie_configured;
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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hose = &pcie1_hose;
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pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
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r = hose->regions;
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pcie_configured = io_sel >= 1;
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if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE connected to slot as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",
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pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BUS,
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CONFIG_SYS_PCIE1_MEM_PHYS,
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CONFIG_SYS_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_IO_BUS,
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CONFIG_SYS_PCIE1_IO_PHYS,
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CONFIG_SYS_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr,
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(int) &pci->cfg_data);
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fsl_pci_init(hose);
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printf ("PCIE on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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first_free_busno=hose->last_busno+1;
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} else {
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printf (" PCIE: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
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#endif
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}
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_OF_BOARD_SETUP)
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extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
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struct pci_controller *hose);
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCIE1
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ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
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#endif
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}
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#endif
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