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![Marek Vasut](/assets/img/avatar_default.png)
Pluck out the remaining CONFIG_HPS_SDR_CTRLCFG_ and put it into the socfpga_sdram_config structure. Signed-off-by: Marek Vasut <marex@denx.de>
746 lines
23 KiB
C
746 lines
23 KiB
C
/*
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* Copyright Altera Corporation (C) 2014-2015
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <div64.h>
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#include <watchdog.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/system_manager.h>
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#include <asm/io.h>
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/*
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* FIXME: This path is temporary until the SDRAM driver gets
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* a proper thorough cleanup.
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*/
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#include "../../../board/altera/socfpga/qts/sdram_config.h"
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DECLARE_GLOBAL_DATA_PTR;
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struct sdram_prot_rule {
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u64 sdram_start; /* SDRAM start address */
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u64 sdram_end; /* SDRAM end address */
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u32 rule; /* SDRAM protection rule number: 0-19 */
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int valid; /* Rule valid or not? 1 - valid, 0 not*/
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u32 security;
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u32 portmask;
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u32 result;
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u32 lo_prot_id;
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u32 hi_prot_id;
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};
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static struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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static struct socfpga_sdr_ctrl *sdr_ctrl =
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(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
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static struct socfpga_sdram_config {
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u32 ctrl_cfg;
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u32 dram_timing1;
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u32 dram_timing2;
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u32 dram_timing3;
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u32 dram_timing4;
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u32 lowpwr_timing;
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u32 dram_odt;
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u32 dram_addrw;
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u32 dram_if_width;
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u32 dram_dev_width;
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u32 dram_intr;
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u32 lowpwr_eq;
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u32 static_cfg;
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u32 ctrl_width;
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u32 cport_width;
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u32 cport_wmap;
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u32 cport_rmap;
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u32 rfifo_cmap;
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u32 wfifo_cmap;
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u32 cport_rdwr;
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u32 port_cfg;
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u32 fpgaport_rst;
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u32 fifo_cfg;
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u32 mp_priority;
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u32 mp_weight0;
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u32 mp_weight1;
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u32 mp_weight2;
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u32 mp_weight3;
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u32 mp_pacing0;
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u32 mp_pacing1;
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u32 mp_pacing2;
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u32 mp_pacing3;
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u32 mp_threshold0;
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u32 mp_threshold1;
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u32 mp_threshold2;
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u32 phy_ctrl0;
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} sdram_config = {
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.ctrl_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
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SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
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SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
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SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
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SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
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SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
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SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
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SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
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SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
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SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
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.dram_timing1 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
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SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
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SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
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SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
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SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
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SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
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SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
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.dram_timing2 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
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SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
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SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
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SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
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SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
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SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
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.dram_timing3 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
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SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
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SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
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SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
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SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
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SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
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.dram_timing4 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
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SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
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SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
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.lowpwr_timing =
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(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
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SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
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SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
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.dram_odt =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
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SDR_CTRLGRP_DRAMODT_READ_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
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SDR_CTRLGRP_DRAMODT_WRITE_LSB),
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.dram_addrw =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
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SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
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SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
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SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
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((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
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SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
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.dram_if_width =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
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SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
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.dram_dev_width =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
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SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
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.dram_intr =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
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SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
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.lowpwr_eq =
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(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
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SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
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.static_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
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SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
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SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
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.ctrl_width =
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(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
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SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
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.cport_width =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
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SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
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.cport_wmap =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
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SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
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.cport_rmap =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
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SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
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.rfifo_cmap =
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(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
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SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
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.wfifo_cmap =
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(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
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SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
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.cport_rdwr =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
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SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
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.port_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
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SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
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.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
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.fifo_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
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SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
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SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
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.mp_priority =
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(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
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SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
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.mp_weight0 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
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.mp_weight1 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
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.mp_weight2 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
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.mp_weight3 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
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.mp_pacing0 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
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SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
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.mp_pacing1 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
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SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
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SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
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.mp_pacing2 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
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SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
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.mp_pacing3 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
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SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
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.mp_threshold0 =
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(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
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.mp_threshold1 =
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(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
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.mp_threshold2 =
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(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
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.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
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};
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/**
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* get_errata_rows() - Up the number of DRAM rows to cover entire address space
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* @cfg: SDRAM controller configuration data
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*
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* SDRAM Failure happens when accessing non-existent memory. Artificially
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* increase the number of rows so that the memory controller thinks it has
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* 4GB of RAM. This function returns such amount of rows.
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*/
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static int get_errata_rows(struct socfpga_sdram_config *cfg)
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{
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/* Define constant for 4G memory - used for SDRAM errata workaround */
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#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
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const unsigned long long memsize = MEMSIZE_4G;
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const unsigned int cs =
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((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
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const unsigned int rows =
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(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
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const unsigned int banks =
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(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
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const unsigned int cols =
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(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
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const unsigned int width = 8;
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unsigned long long newrows;
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int bits, inewrowslog2;
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debug("workaround rows - memsize %lld\n", memsize);
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debug("workaround rows - cs %d\n", cs);
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debug("workaround rows - width %d\n", width);
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debug("workaround rows - rows %d\n", rows);
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debug("workaround rows - banks %d\n", banks);
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debug("workaround rows - cols %d\n", cols);
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newrows = lldiv(memsize, cs * (width / 8));
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debug("rows workaround - term1 %lld\n", newrows);
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newrows = lldiv(newrows, (1 << banks) * (1 << cols));
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debug("rows workaround - term2 %lld\n", newrows);
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/*
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* Compute the hamming weight - same as number of bits set.
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* Need to see if result is ordinal power of 2 before
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* attempting log2 of result.
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*/
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bits = generic_hweight32(newrows);
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debug("rows workaround - bits %d\n", bits);
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if (bits != 1) {
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printf("SDRAM workaround failed, bits set %d\n", bits);
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return rows;
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}
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if (newrows > UINT_MAX) {
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printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
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return rows;
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}
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inewrowslog2 = __ilog2(newrows);
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debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
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if (inewrowslog2 == -1) {
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printf("SDRAM workaround failed, newrows %lld\n", newrows);
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return rows;
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}
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return inewrowslog2;
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}
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/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
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static void sdram_set_rule(struct sdram_prot_rule *prule)
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{
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uint32_t lo_addr_bits;
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uint32_t hi_addr_bits;
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int ruleno = prule->rule;
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/* Select the rule */
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writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
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/* Obtain the address bits */
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lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
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hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
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debug("sdram set rule start %x, %lld\n", lo_addr_bits,
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prule->sdram_start);
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debug("sdram set rule end %x, %lld\n", hi_addr_bits,
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prule->sdram_end);
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/* Set rule addresses */
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writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
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/* Set rule protection ids */
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writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
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&sdr_ctrl->prot_rule_id);
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/* Set the rule data */
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writel(prule->security | (prule->valid << 2) |
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(prule->portmask << 3) | (prule->result << 13),
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&sdr_ctrl->prot_rule_data);
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/* write the rule */
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writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
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/* Set rule number to 0 by default */
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writel(0, &sdr_ctrl->prot_rule_rdwr);
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}
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static void sdram_get_rule(struct sdram_prot_rule *prule)
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{
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uint32_t addr;
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uint32_t id;
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uint32_t data;
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int ruleno = prule->rule;
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/* Read the rule */
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writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
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writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
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/* Get the addresses */
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addr = readl(&sdr_ctrl->prot_rule_addr);
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prule->sdram_start = (addr & 0xFFF) << 20;
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prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
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/* Get the configured protection IDs */
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id = readl(&sdr_ctrl->prot_rule_id);
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prule->lo_prot_id = id & 0xFFF;
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|
prule->hi_prot_id = (id >> 12) & 0xFFF;
|
|
|
|
/* Get protection data */
|
|
data = readl(&sdr_ctrl->prot_rule_data);
|
|
|
|
prule->security = data & 0x3;
|
|
prule->valid = (data >> 2) & 0x1;
|
|
prule->portmask = (data >> 3) & 0x3FF;
|
|
prule->result = (data >> 13) & 0x1;
|
|
}
|
|
|
|
static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
|
|
{
|
|
struct sdram_prot_rule rule;
|
|
int rules;
|
|
|
|
/* Start with accepting all SDRAM transaction */
|
|
writel(0x0, &sdr_ctrl->protport_default);
|
|
|
|
/* Clear all protection rules for warm boot case */
|
|
memset(&rule, 0, sizeof(struct sdram_prot_rule));
|
|
|
|
for (rules = 0; rules < 20; rules++) {
|
|
rule.rule = rules;
|
|
sdram_set_rule(&rule);
|
|
}
|
|
|
|
/* new rule: accept SDRAM */
|
|
rule.sdram_start = sdram_start;
|
|
rule.sdram_end = sdram_end;
|
|
rule.lo_prot_id = 0x0;
|
|
rule.hi_prot_id = 0xFFF;
|
|
rule.portmask = 0x3FF;
|
|
rule.security = 0x3;
|
|
rule.result = 0;
|
|
rule.valid = 1;
|
|
rule.rule = 0;
|
|
|
|
/* set new rule */
|
|
sdram_set_rule(&rule);
|
|
|
|
/* default rule: reject everything */
|
|
writel(0x3ff, &sdr_ctrl->protport_default);
|
|
}
|
|
|
|
static void sdram_dump_protection_config(void)
|
|
{
|
|
struct sdram_prot_rule rule;
|
|
int rules;
|
|
|
|
debug("SDRAM Prot rule, default %x\n",
|
|
readl(&sdr_ctrl->protport_default));
|
|
|
|
for (rules = 0; rules < 20; rules++) {
|
|
sdram_get_rule(&rule);
|
|
debug("Rule %d, rules ...\n", rules);
|
|
debug(" sdram start %llx\n", rule.sdram_start);
|
|
debug(" sdram end %llx\n", rule.sdram_end);
|
|
debug(" low prot id %d, hi prot id %d\n",
|
|
rule.lo_prot_id,
|
|
rule.hi_prot_id);
|
|
debug(" portmask %x\n", rule.portmask);
|
|
debug(" security %d\n", rule.security);
|
|
debug(" result %d\n", rule.result);
|
|
debug(" valid %d\n", rule.valid);
|
|
}
|
|
}
|
|
|
|
/* Function to write to register and verify the write */
|
|
static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
|
|
{
|
|
#ifndef SDRAM_MMR_SKIP_VERIFY
|
|
unsigned reg_value1;
|
|
#endif
|
|
debug(" Write - Address ");
|
|
debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
|
|
/* Write to register */
|
|
writel(reg_value, addr);
|
|
#ifndef SDRAM_MMR_SKIP_VERIFY
|
|
debug(" Read and verify...");
|
|
/* Read back the wrote value */
|
|
reg_value1 = readl(addr);
|
|
/* Indicate failure if value not matched */
|
|
if (reg_value1 != reg_value) {
|
|
debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
|
|
(u32)addr, reg_value, reg_value1);
|
|
return 1;
|
|
}
|
|
debug("correct!\n");
|
|
#endif /* SDRAM_MMR_SKIP_VERIFY */
|
|
return 0;
|
|
}
|
|
|
|
static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg)
|
|
{
|
|
const u32 csbits =
|
|
((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
|
|
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
|
|
u32 addrorder =
|
|
(cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
|
|
SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
|
|
|
|
u32 ctrl_cfg = cfg->ctrl_cfg;
|
|
|
|
debug("\nConfiguring CTRLCFG\n");
|
|
|
|
/*
|
|
* SDRAM Failure When Accessing Non-Existent Memory
|
|
* Set the addrorder field of the SDRAM control register
|
|
* based on the CSBITs setting.
|
|
*/
|
|
if (csbits == 1) {
|
|
if (addrorder != 0)
|
|
debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
|
|
addrorder = 0;
|
|
} else if (csbits == 2) {
|
|
if (addrorder != 2)
|
|
debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
|
|
addrorder = 2;
|
|
}
|
|
|
|
ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
|
|
ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
|
|
|
|
writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
|
|
}
|
|
|
|
static void set_sdr_dram_timing(struct socfpga_sdram_config *cfg)
|
|
{
|
|
debug("Configuring DRAMTIMING1\n");
|
|
writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
|
|
|
|
debug("Configuring DRAMTIMING2\n");
|
|
writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
|
|
|
|
debug("Configuring DRAMTIMING3\n");
|
|
writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
|
|
|
|
debug("Configuring DRAMTIMING4\n");
|
|
writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
|
|
|
|
debug("Configuring LOWPWRTIMING\n");
|
|
writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
|
|
}
|
|
|
|
static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg)
|
|
{
|
|
/*
|
|
* SDRAM Failure When Accessing Non-Existent Memory
|
|
* Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
|
|
* log2(number of chip select bits). Since there's only
|
|
* 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
|
|
* which is the same as "chip selects" - 1.
|
|
*/
|
|
const int rows = get_errata_rows(cfg);
|
|
u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
|
|
|
|
debug("Configuring DRAMADDRW\n");
|
|
writel(dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB),
|
|
&sdr_ctrl->dram_addrw);
|
|
}
|
|
|
|
static void set_sdr_static_cfg(struct socfpga_sdram_config *cfg)
|
|
{
|
|
debug("Configuring STATICCFG\n");
|
|
writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
|
|
}
|
|
|
|
static void set_sdr_fifo_cfg(struct socfpga_sdram_config *cfg)
|
|
{
|
|
debug("Configuring FIFOCFG\n");
|
|
writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
|
|
}
|
|
|
|
static void set_sdr_mp_weight(struct socfpga_sdram_config *cfg)
|
|
{
|
|
debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
|
|
writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
|
|
writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
|
|
writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
|
|
writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
|
|
}
|
|
|
|
static void set_sdr_mp_pacing(struct socfpga_sdram_config *cfg)
|
|
{
|
|
debug("Configuring MPPACING_MPPACING_0\n");
|
|
writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
|
|
writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
|
|
writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
|
|
writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
|
|
}
|
|
|
|
static void set_sdr_mp_threshold(struct socfpga_sdram_config *cfg)
|
|
{
|
|
debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
|
|
writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
|
|
writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
|
|
writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
|
|
}
|
|
|
|
/* Function to initialize SDRAM MMR */
|
|
unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
|
|
{
|
|
unsigned long status = 0;
|
|
struct socfpga_sdram_config *cfg = &sdram_config;
|
|
const unsigned int rows =
|
|
(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
|
|
SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
|
|
|
|
writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
|
|
|
|
set_sdr_ctrlcfg(cfg);
|
|
set_sdr_dram_timing(cfg);
|
|
set_sdr_addr_rw(cfg);
|
|
|
|
debug("Configuring DRAMIFWIDTH\n");
|
|
writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
|
|
|
|
debug("Configuring DRAMDEVWIDTH\n");
|
|
writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
|
|
|
|
debug("Configuring LOWPWREQ\n");
|
|
writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
|
|
|
|
debug("Configuring DRAMINTR\n");
|
|
writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
|
|
|
|
set_sdr_static_cfg(cfg);
|
|
|
|
debug("Configuring CTRLWIDTH\n");
|
|
writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
|
|
|
|
debug("Configuring PORTCFG\n");
|
|
writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
|
|
|
|
set_sdr_fifo_cfg(cfg);
|
|
|
|
debug("Configuring MPPRIORITY\n");
|
|
writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
|
|
|
|
set_sdr_mp_weight(cfg);
|
|
set_sdr_mp_pacing(cfg);
|
|
set_sdr_mp_threshold(cfg);
|
|
|
|
debug("Configuring PHYCTRL_PHYCTRL_0\n");
|
|
writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
|
|
|
|
debug("Configuring CPORTWIDTH\n");
|
|
writel(cfg->cport_width, &sdr_ctrl->cport_width);
|
|
|
|
debug("Configuring CPORTWMAP\n");
|
|
writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
|
|
|
|
debug("Configuring CPORTRMAP\n");
|
|
writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
|
|
|
|
debug("Configuring RFIFOCMAP\n");
|
|
writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
|
|
|
|
debug("Configuring WFIFOCMAP\n");
|
|
writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
|
|
|
|
debug("Configuring CPORTRDWR\n");
|
|
writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
|
|
|
|
debug("Configuring DRAMODT\n");
|
|
writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
|
|
|
|
/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
|
|
writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
|
|
|
|
/* only enable if the FPGA is programmed */
|
|
if (fpgamgr_test_fpga_ready()) {
|
|
if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
|
|
cfg->fpgaport_rst) == 1) {
|
|
status = 1;
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
/* Restore the SDR PHY Register if valid */
|
|
if (sdr_phy_reg != 0xffffffff)
|
|
writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
|
|
|
|
/* Final step - apply configuration changes */
|
|
debug("Configuring STATICCFG\n");
|
|
clrsetbits_le32(&sdr_ctrl->static_cfg,
|
|
SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
|
|
1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
|
|
|
|
sdram_set_protection_config(0, sdram_calculate_size());
|
|
|
|
sdram_dump_protection_config();
|
|
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* To calculate SDRAM device size based on SDRAM controller parameters.
|
|
* Size is specified in bytes.
|
|
*
|
|
* NOTE:
|
|
* This function is compiled and linked into the preloader and
|
|
* Uboot (there may be others). So if this function changes, the Preloader
|
|
* and UBoot must be updated simultaneously.
|
|
*/
|
|
unsigned long sdram_calculate_size(void)
|
|
{
|
|
unsigned long temp;
|
|
unsigned long row, bank, col, cs, width;
|
|
|
|
temp = readl(&sdr_ctrl->dram_addrw);
|
|
col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
|
|
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
|
|
|
|
/* SDRAM Failure When Accessing Non-Existent Memory
|
|
* Use ROWBITS from Quartus/QSys to calculate SDRAM size
|
|
* since the FB specifies we modify ROWBITs to work around SDRAM
|
|
* controller issue.
|
|
*
|
|
* If the stored handoff value for rows is 0, it probably means
|
|
* the preloader is older than UBoot. Use the
|
|
* #define from the SOCEDS Tools per Crucible review
|
|
* uboot-socfpga-204. Note that this is not a supported
|
|
* configuration and is not tested. The customer
|
|
* should be using preloader and uboot built from the
|
|
* same tag.
|
|
*/
|
|
row = readl(&sysmgr_regs->iswgrp_handoff[4]);
|
|
if (row == 0)
|
|
row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
|
|
/* If the stored handoff value for rows is greater than
|
|
* the field width in the sdr.dramaddrw register then
|
|
* something is very wrong. Revert to using the the #define
|
|
* value handed off by the SOCEDS tool chain instead of
|
|
* using a broken value.
|
|
*/
|
|
if (row > 31)
|
|
row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
|
|
|
|
bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
|
|
SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
|
|
|
|
/* SDRAM Failure When Accessing Non-Existent Memory
|
|
* Use CSBITs from Quartus/QSys to calculate SDRAM size
|
|
* since the FB specifies we modify CSBITs to work around SDRAM
|
|
* controller issue.
|
|
*/
|
|
cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
|
|
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
|
|
cs += 1;
|
|
|
|
cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
|
|
|
|
width = readl(&sdr_ctrl->dram_if_width);
|
|
/* ECC would not be calculated as its not addressible */
|
|
if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
|
|
width = 32;
|
|
if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
|
|
width = 16;
|
|
|
|
/* calculate the SDRAM size base on this info */
|
|
temp = 1 << (row + bank + col);
|
|
temp = temp * cs * (width / 8);
|
|
|
|
debug("sdram_calculate_memory returns %ld\n", temp);
|
|
|
|
return temp;
|
|
}
|