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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
392 lines
9.7 KiB
C
392 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/cache.h>
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#include <asm/system.h>
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#include <tsec.h>
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#include <netdev.h>
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#include <fsl_esdhc.h>
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#include <config.h>
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#include <fsl_wdog.h>
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#include "fsl_epu.h"
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#define DCSR_RCPM2_BLOCK_OFFSET 0x223000
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#define DCSR_RCPM2_CPMFSMCR0 0x400
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#define DCSR_RCPM2_CPMFSMSR0 0x404
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#define DCSR_RCPM2_CPMFSMCR1 0x414
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#define DCSR_RCPM2_CPMFSMSR1 0x418
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#define CPMFSMSR_FSM_STATE_MASK 0x7f
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_DCACHE_OFF
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/*
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* Bit[1] of the descriptor indicates the descriptor type,
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* and bit[0] indicates whether the descriptor is valid.
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*/
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#define PMD_TYPE_TABLE 0x3
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#define PMD_TYPE_SECT 0x1
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/* AttrIndx[2:0] */
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#define PMD_ATTRINDX(t) ((t) << 2)
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/* Section */
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#define PMD_SECT_AF (1 << 10)
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#define BLOCK_SIZE_L1 (1UL << 30)
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#define BLOCK_SIZE_L2 (1UL << 21)
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/* TTBCR flags */
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#define TTBCR_EAE (1 << 31)
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#define TTBCR_T0SZ(x) ((x) << 0)
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#define TTBCR_T1SZ(x) ((x) << 16)
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#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
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#define TTBCR_IRGN0_NC (0 << 8)
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#define TTBCR_IRGN0_WBWA (1 << 8)
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#define TTBCR_IRGN0_WT (2 << 8)
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#define TTBCR_IRGN0_WBNWA (3 << 8)
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#define TTBCR_IRGN0_MASK (3 << 8)
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#define TTBCR_ORGN0_NC (0 << 10)
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#define TTBCR_ORGN0_WBWA (1 << 10)
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#define TTBCR_ORGN0_WT (2 << 10)
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#define TTBCR_ORGN0_WBNWA (3 << 10)
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#define TTBCR_ORGN0_MASK (3 << 10)
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#define TTBCR_SHARED_NON (0 << 12)
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#define TTBCR_SHARED_OUTER (2 << 12)
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#define TTBCR_SHARED_INNER (3 << 12)
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#define TTBCR_EPD0 (0 << 7)
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#define TTBCR (TTBCR_SHARED_NON | \
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TTBCR_ORGN0_NC | \
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TTBCR_IRGN0_NC | \
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TTBCR_USING_TTBR0 | \
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TTBCR_EAE)
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/*
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* Memory region attributes for LPAE (defined in pgtable):
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*
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* n = AttrIndx[2:0]
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*
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* n MAIR
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* UNCACHED 000 00000000
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* BUFFERABLE 001 01000100
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* DEV_WC 001 01000100
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* WRITETHROUGH 010 10101010
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* WRITEBACK 011 11101110
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* DEV_CACHED 011 11101110
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* DEV_SHARED 100 00000100
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* DEV_NONSHARED 100 00000100
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* unused 101
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* unused 110
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* WRITEALLOC 111 11111111
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*/
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#define MT_MAIR0 0xeeaa4400
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#define MT_MAIR1 0xff000004
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#define MT_STRONLY_ORDER 0
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#define MT_NORMAL_NC 1
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#define MT_DEVICE_MEM 4
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#define MT_NORMAL 7
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/* The phy_addr must be aligned to 4KB */
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static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
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{
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u32 value = phy_addr | PMD_TYPE_TABLE;
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page_table[2 * index] = value;
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page_table[2 * index + 1] = 0;
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}
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/* The phy_addr must be aligned to 4KB */
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static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
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u32 memory_type)
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{
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u64 value;
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value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
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value |= PMD_ATTRINDX(memory_type);
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page_table[2 * index] = value & 0xFFFFFFFF;
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page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
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}
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/*
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* Start MMU after DDR is available, we create MMU table in DRAM.
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* The base address of TTLB is gd->arch.tlb_addr. We use two
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* levels of translation tables here to cover 40-bit address space.
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*
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* The TTLBs are located at PHY 2G~4G.
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*
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* VA mapping:
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*
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* ------- <---- 0GB
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* | |
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* | |
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* |-------| <---- 0x24000000
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* |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
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* |-------| <---- 0x300000000
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* | |
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* |-------| <---- 0x34000000
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* |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
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* |-------| <---- 0x40000000
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* | |
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* |-------| <---- 0x80000000 DDR0 space start
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* |\\\\\\\|
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*.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
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* |\\\\\\\|
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* ------- <---- 4GB DDR0 space end
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*/
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static void mmu_setup(void)
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{
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u32 *level0_table = (u32 *)gd->arch.tlb_addr;
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u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
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u64 va_start = 0;
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u32 reg;
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int i;
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/* Level 0 Table 2-3 are used to map DDR */
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set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
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set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
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/* Level 0 Table 1 is used to map device */
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set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
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/* Level 0 Table 0 is used to map device including PCIe MEM */
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set_pgtable(level0_table, 0, (u32)level1_table);
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/* Level 1 has 512 entries */
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for (i = 0; i < 512; i++) {
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/* Mapping for PCIe 1 */
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if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
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va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
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CONFIG_SYS_PCIE_MMAP_SIZE))
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set_pgsection(level1_table, i,
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CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
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MT_DEVICE_MEM);
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/* Mapping for PCIe 2 */
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else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
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va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
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CONFIG_SYS_PCIE_MMAP_SIZE))
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set_pgsection(level1_table, i,
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CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
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MT_DEVICE_MEM);
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else
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set_pgsection(level1_table, i,
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va_start,
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MT_DEVICE_MEM);
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va_start += BLOCK_SIZE_L2;
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}
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asm volatile("dsb sy;isb");
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asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
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: : "r" (TTBCR) : "memory");
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asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
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: : "r" ((u32)level0_table), "r" (0) : "memory");
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asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
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: : "r" (MT_MAIR0) : "memory");
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asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
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: : "r" (MT_MAIR1) : "memory");
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/* Set the access control to all-supervisor */
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asm volatile("mcr p15, 0, %0, c3, c0, 0"
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: : "r" (~0));
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/* Enable the mmu */
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reg = get_cr();
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set_cr(reg | CR_M);
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}
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/*
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* This function is called from lib/board.c. It recreates MMU
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* table in main memory. MMU and i/d-cache are enabled here.
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*/
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void enable_caches(void)
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{
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/* Invalidate all TLB */
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mmu_page_table_flush(gd->arch.tlb_addr,
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gd->arch.tlb_addr + gd->arch.tlb_size);
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/* Set up and enable mmu */
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mmu_setup();
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/* Invalidate & Enable d-cache */
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invalidate_dcache_all();
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set_cr(get_cr() | CR_C);
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}
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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uint get_svr(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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return in_be32(&gur->svr);
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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char buf1[32], buf2[32];
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int svr, major, minor, ver, i;
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svr = in_be32(&gur->svr);
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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puts("CPU: Freescale LayerScape ");
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ver = SVR_SOC_VER(svr);
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switch (ver) {
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case SOC_VER_SLS1020:
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puts("SLS1020");
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break;
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case SOC_VER_LS1020:
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puts("LS1020");
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break;
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case SOC_VER_LS1021:
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puts("LS1021");
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break;
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case SOC_VER_LS1022:
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puts("LS1022");
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break;
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default:
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puts("Unknown");
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break;
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}
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if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
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puts("E");
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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puts("Clock Configuration:");
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printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
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printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
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printf("DDR:%-4s MHz (%s MT/s data rate), ",
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strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
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puts("\n");
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/* Display the RCW, so that no one gets confused as to what RCW
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* we're actually using for this boot.
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*/
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puts("Reset Configuration Word (RCW):");
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for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
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u32 rcw = in_be32(&gur->rcwsr[i]);
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if ((i % 4) == 0)
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printf("\n %08x:", i * 4);
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printf(" %08x", rcw);
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}
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puts("\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_FSL_ESDHC
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int cpu_mmc_init(bd_t *bis)
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{
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return fsl_esdhc_mmc_init(bis);
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_TSEC_ENET
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tsec_standard_init(bis);
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#endif
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return 0;
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}
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int arch_cpu_init(void)
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{
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void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
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void *rcpm2_base =
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(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
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struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
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u32 state;
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/*
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* The RCPM FSM state may not be reset after power-on.
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* So, reset them.
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*/
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state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
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CPMFSMSR_FSM_STATE_MASK;
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if (state != 0) {
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out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
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out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
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}
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state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
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CPMFSMSR_FSM_STATE_MASK;
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if (state != 0) {
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out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
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out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
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}
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/*
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* After wakeup from deep sleep, Clear EPU registers
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* as early as possible to prevent from possible issue.
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* It's also safe to clear at normal boot.
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*/
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fsl_epu_clean(epu_base);
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setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
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return 0;
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}
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#ifdef CONFIG_ARMV7_NONSEC
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/* Set the address at which the secondary core starts from.*/
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void smp_set_core_boot_addr(unsigned long addr, int corenr)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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out_be32(&gur->scratchrw[0], addr);
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}
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/* Release the secondary core from holdoff state and kick it */
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void smp_kick_all_cpus(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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out_be32(&gur->brrl, 0x2);
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/*
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* LS1 STANDBYWFE is not captured outside the ARM module in the soc.
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* So add a delay to wait bootrom execute WFE.
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*/
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udelay(1);
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asm volatile("sev");
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}
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#endif
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void reset_cpu(ulong addr)
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{
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struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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clrbits_be16(&wdog->wcr, WCR_SRS);
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while (1) {
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/*
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* Let the watchdog trigger
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*/
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}
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}
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void arch_preboot_os(void)
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{
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unsigned long ctrl;
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/* Disable PL1 Physical Timer */
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asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
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ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
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asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
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}
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