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https://github.com/brain-hackers/u-boot-brain
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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
180 lines
2.3 KiB
ArmAsm
180 lines
2.3 KiB
ArmAsm
/*
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* Miscellaneous assembly functions.
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*
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* Copyright (C) 2001 - 2007 Tensilica Inc.
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* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
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*
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* Chris Zankel <chris@zankel.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/linkage.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheasm.h>
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/*
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* void __invalidate_icache_page(ulong start)
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*/
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ENTRY(__invalidate_icache_page)
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abi_entry
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___invalidate_icache_page a2 a3
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isync
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abi_ret
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ENDPROC(__invalidate_icache_page)
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/*
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* void __invalidate_dcache_page(ulong start)
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*/
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ENTRY(__invalidate_dcache_page)
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abi_entry
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___invalidate_dcache_page a2 a3
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dsync
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abi_ret
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ENDPROC(__invalidate_dcache_page)
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/*
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* void __flush_invalidate_dcache_page(ulong start)
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*/
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ENTRY(__flush_invalidate_dcache_page)
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abi_entry
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___flush_invalidate_dcache_page a2 a3
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dsync
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abi_ret
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ENDPROC(__flush_invalidate_dcache_page)
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/*
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* void __flush_dcache_page(ulong start)
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*/
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ENTRY(__flush_dcache_page)
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abi_entry
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___flush_dcache_page a2 a3
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dsync
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abi_ret
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ENDPROC(__flush_dcache_page)
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/*
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* void __invalidate_icache_range(ulong start, ulong size)
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*/
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ENTRY(__invalidate_icache_range)
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abi_entry
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___invalidate_icache_range a2 a3 a4
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isync
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abi_ret
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ENDPROC(__invalidate_icache_range)
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/*
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* void __flush_invalidate_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__flush_invalidate_dcache_range)
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abi_entry
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___flush_invalidate_dcache_range a2 a3 a4
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dsync
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abi_ret
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ENDPROC(__flush_invalidate_dcache_range)
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/*
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* void _flush_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__flush_dcache_range)
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abi_entry
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___flush_dcache_range a2 a3 a4
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dsync
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abi_ret
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ENDPROC(__flush_dcache_range)
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/*
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* void _invalidate_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__invalidate_dcache_range)
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abi_entry
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___invalidate_dcache_range a2 a3 a4
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abi_ret
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ENDPROC(__invalidate_dcache_range)
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/*
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* void _invalidate_icache_all(void)
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*/
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ENTRY(__invalidate_icache_all)
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abi_entry
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___invalidate_icache_all a2 a3
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isync
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abi_ret
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ENDPROC(__invalidate_icache_all)
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/*
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* void _flush_invalidate_dcache_all(void)
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*/
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ENTRY(__flush_invalidate_dcache_all)
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abi_entry
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___flush_invalidate_dcache_all a2 a3
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dsync
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abi_ret
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ENDPROC(__flush_invalidate_dcache_all)
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/*
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* void _invalidate_dcache_all(void)
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*/
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ENTRY(__invalidate_dcache_all)
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abi_entry
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___invalidate_dcache_all a2 a3
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dsync
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abi_ret
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ENDPROC(__invalidate_dcache_all)
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