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https://github.com/brain-hackers/u-boot-brain
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340d1d3a0e
It's a trim version of mx6q_4x_mt41j128.cfg. It just removed the related settings for DDR Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
59 lines
1.4 KiB
INI
59 lines
1.4 KiB
INI
/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* Jason Liu <r64343@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* set the default clock gate to save power */
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DATA 4 0x020c4068 0x00C03F3F
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DATA 4 0x020c406c 0x0030FC03
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DATA 4 0x020c4070 0x0FFFC000
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DATA 4 0x020c4074 0x3FF00000
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DATA 4 0x020c4078 0x00FFF300
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DATA 4 0x020c407c 0x0F0000C3
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DATA 4 0x020c4080 0x000003FF
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4 0x020e0010 0xF00000CF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4 0x020e0018 0x007F007F
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DATA 4 0x020e001c 0x007F007F
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/*
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* Setup CCM_CCOSR register as follows:
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*
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* cko1_en = 1 --> CKO1 enabled
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* cko1_div = 111 --> divide by 8
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* cko1_sel = 1011 --> ahb_clk_root
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*
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* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
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*/
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DATA 4 0x020c4060 0x000000fb
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