Marek Vasut 75df748b87 ARM: dts: stm32: Disable SDMMC1 CKIN feedback clock ... The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter or without one on the SDMMC1 interface. Because the SDMMC1 interface is limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback clock to permit operation of the same U-Boot image on both SoM with and without voltage level shifter. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>		2020-12-09 10:57:50 +01:00
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arc
arm	ARM: dts: stm32: Disable SDMMC1 CKIN feedback clock	2020-12-09 10:57:50 +01:00
m68k	arch: Move NEEDS_MANUAL_RELOC symbol to Kconfig	2020-11-04 10:13:44 -05:00
microblaze	microblaze: Enable GCC garbage collector for full U-Boot	2020-11-20 10:42:53 +01:00
mips	mips: octeon: tools: Add update_octeon_header tool	2020-11-30 18:32:09 +01:00
nds32
nios2
powerpc	board: Rename uclass to sysinfo	2020-11-06 10:18:20 +08:00
riscv	riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller	2020-11-28 08:30:41 +01:00
sandbox	patman status subcommand to collect tags from Patchwork	2020-11-06 11:27:14 -05:00
sh
x86	x86: coral: Update smbios tables to latest definition	2020-11-10 09:44:20 +08:00
xtensa
.gitignore
Kconfig	patman status subcommand to collect tags from Patchwork	2020-11-06 11:27:14 -05:00
u-boot-elf.lds