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https://github.com/brain-hackers/u-boot-brain
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950eaf6230
It is difficult to track down fail to boot issues in the mxs SPL. Implement the following to make it easier: - Add debug outputs to allow tracing of SPL progress in order to track where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must be defined to enable debug output in SPL - Add TODO comments where it is not clear if the code is doing what it is meant to be doing, even tough the board boots properly (these comments refer to existing code, not to any code added by this patch) Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
361 lines
9.7 KiB
C
361 lines
9.7 KiB
C
/*
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* Freescale i.MX28 RAM init
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/compiler.h>
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#include "mxs_init.h"
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static uint32_t dram_vals[] = {
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/*
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* i.MX28 DDR2 at 200MHz
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*/
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#if defined(CONFIG_MX28)
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000100, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00010101, 0x01010101,
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0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
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0x00000100, 0x00000100, 0x00000000, 0x00000002,
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0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
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0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
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0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
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0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
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0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
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0x00000003, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000612, 0x01000F02,
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0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
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0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
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0x07000300, 0x07400300, 0x07400300, 0x00000005,
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0x00000000, 0x00000000, 0x01000000, 0x01020408,
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0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
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0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
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0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00010000, 0x00030404,
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0x00000003, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x01010000,
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0x01000000, 0x03030000, 0x00010303, 0x01020202,
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0x00000000, 0x02040303, 0x21002103, 0x00061200,
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0x06120612, 0x04420442, 0x04420442, 0x00040004,
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0x00040004, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0xffffffff
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/*
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* i.MX23 DDR at 133MHz
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*/
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#elif defined(CONFIG_MX23)
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0x01010001, 0x00010100, 0x01000101, 0x00000001,
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0x00000101, 0x00000000, 0x00010000, 0x01000001,
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0x00000000, 0x00000001, 0x07000200, 0x00070202,
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0x02020000, 0x04040a01, 0x00000201, 0x02040000,
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0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
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0x02061521, 0x0000000a, 0x00080008, 0x00200020,
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0x00200020, 0x00200020, 0x000003f7, 0x00000000,
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0x00000000, 0x00000020, 0x00000020, 0x00c80000,
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0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
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0x00000101, 0x00040001, 0x00000000, 0x00000000,
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0x00010000
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#else
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#error Unsupported memory initialization
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#endif
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};
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__weak void mxs_adjust_memory_params(uint32_t *dram_vals)
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{
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debug("SPL: Using default SDRAM parameters\n");
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}
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#ifdef CONFIG_MX28
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static void initialize_dram_values(void)
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{
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int i;
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debug("SPL: Setting mx28 board specific SDRAM parameters\n");
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mxs_adjust_memory_params(dram_vals);
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debug("SPL: Applying SDRAM parameters\n");
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for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
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writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
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}
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#else
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static void initialize_dram_values(void)
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{
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int i;
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debug("SPL: Setting mx23 board specific SDRAM parameters\n");
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mxs_adjust_memory_params(dram_vals);
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/*
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* HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
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* per FSL bootlets code.
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*
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* mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
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* "reserved".
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* HW_DRAM_CTL8 is setup as the last element.
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* So skip the initialization of these HW_DRAM_CTL registers.
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*/
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debug("SPL: Applying SDRAM parameters\n");
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for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
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if (i == 8 || i == 27 || i == 28 || i == 35)
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continue;
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writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
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}
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/*
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* Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
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* element to be set
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*/
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writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
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}
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#endif
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static void mxs_mem_init_clock(void)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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#if defined(CONFIG_MX23)
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/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
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const unsigned char divider = 33;
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#elif defined(CONFIG_MX28)
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/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
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const unsigned char divider = 21;
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#endif
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debug("SPL: Initialising FRAC0\n");
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/* Gate EMI clock */
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writeb(CLKCTRL_FRAC_CLKGATE,
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&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
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/* Set fractional divider for ref_emi */
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writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
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&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
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/* Ungate EMI clock */
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writeb(CLKCTRL_FRAC_CLKGATE,
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&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
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early_delay(11000);
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/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
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writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
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(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
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&clkctrl_regs->hw_clkctrl_emi);
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/* Unbypass EMI */
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writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
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&clkctrl_regs->hw_clkctrl_clkseq_clr);
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early_delay(10000);
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debug("SPL: FRAC0 Initialised\n");
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}
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static void mxs_mem_setup_cpu_and_hbus(void)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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debug("SPL: Setting CPU and HBUS clock frequencies\n");
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/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
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* and ungate CPU clock */
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writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
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(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
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/* Set CPU bypass */
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writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
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&clkctrl_regs->hw_clkctrl_clkseq_set);
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/* HBUS = 151MHz */
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writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
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writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
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&clkctrl_regs->hw_clkctrl_hbus_clr);
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early_delay(10000);
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/* CPU clock divider = 1 */
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clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
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CLKCTRL_CPU_DIV_CPU_MASK, 1);
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/* Disable CPU bypass */
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writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
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&clkctrl_regs->hw_clkctrl_clkseq_clr);
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early_delay(15000);
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}
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static void mxs_mem_setup_vdda(void)
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{
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struct mxs_power_regs *power_regs =
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(struct mxs_power_regs *)MXS_POWER_BASE;
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debug("SPL: Configuring VDDA\n");
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writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
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(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
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POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
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&power_regs->hw_power_vddactrl);
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}
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uint32_t mxs_mem_get_size(void)
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{
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uint32_t sz, da;
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uint32_t *vt = (uint32_t *)0x20;
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/* The following is "subs pc, r14, #4", used as return from DABT. */
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const uint32_t data_abort_memdetect_handler = 0xe25ef004;
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/* Replace the DABT handler. */
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da = vt[4];
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vt[4] = data_abort_memdetect_handler;
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sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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/* Restore the old DABT handler. */
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vt[4] = da;
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return sz;
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}
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#ifdef CONFIG_MX23
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static void mx23_mem_setup_vddmem(void)
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{
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struct mxs_power_regs *power_regs =
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(struct mxs_power_regs *)MXS_POWER_BASE;
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debug("SPL: Setting mx23 VDDMEM\n");
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/* We must wait before and after disabling the current limiter! */
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early_delay(10000);
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clrbits_le32(&power_regs->hw_power_vddmemctrl,
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POWER_VDDMEMCTRL_ENABLE_ILIMIT);
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early_delay(10000);
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}
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static void mx23_mem_init(void)
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{
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debug("SPL: Initialising mx23 SDRAM Controller\n");
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/*
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* Reset/ungate the EMI block. This is essential, otherwise the system
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* suffers from memory instability. This thing is mx23 specific and is
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* no longer present on mx28.
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*/
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mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
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mx23_mem_setup_vddmem();
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/*
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* Configure the DRAM registers
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*/
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/* Clear START and SREFRESH bit from DRAM_CTL8 */
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clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
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initialize_dram_values();
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/* Set START bit in DRAM_CTL8 */
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setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
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clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
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/* Wait for EMI_STAT bit DRAM_HALTED */
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for (;;) {
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if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
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break;
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early_delay(1000);
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}
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/* Adjust EMI port priority. */
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clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
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early_delay(20000);
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setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
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setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
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}
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#endif
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#ifdef CONFIG_MX28
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static void mx28_mem_init(void)
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{
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struct mxs_pinctrl_regs *pinctrl_regs =
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(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
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debug("SPL: Initialising mx28 SDRAM Controller\n");
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/* Set DDR2 mode */
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writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
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&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
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/*
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* Configure the DRAM registers
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*/
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/* Clear START bit from DRAM_CTL16 */
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clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
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initialize_dram_values();
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/* Clear SREFRESH bit from DRAM_CTL17 */
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clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
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/* Set START bit in DRAM_CTL16 */
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setbits_le32(MXS_DRAM_BASE + 0x40, 1);
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/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
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while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
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;
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}
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#endif
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void mxs_mem_init(void)
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{
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early_delay(11000);
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mxs_mem_init_clock();
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mxs_mem_setup_vdda();
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#if defined(CONFIG_MX23)
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mx23_mem_init();
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#elif defined(CONFIG_MX28)
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mx28_mem_init();
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#endif
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early_delay(10000);
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mxs_mem_setup_cpu_and_hbus();
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}
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