mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
950eaf6230
It is difficult to track down fail to boot issues in the mxs SPL. Implement the following to make it easier: - Add debug outputs to allow tracing of SPL progress in order to track where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must be defined to enable debug output in SPL - Add TODO comments where it is not clear if the code is doing what it is meant to be doing, even tough the board boots properly (these comments refer to existing code, not to any code added by this patch) Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
80 lines
2.3 KiB
C
80 lines
2.3 KiB
C
/*
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* Freescale i.MX28 Battery measurement init
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include "mxs_init.h"
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void mxs_lradc_init(void)
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{
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struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
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debug("SPL: Initialisating LRADC\n");
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writel(LRADC_CTRL0_SFTRST, ®s->hw_lradc_ctrl0_clr);
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writel(LRADC_CTRL0_CLKGATE, ®s->hw_lradc_ctrl0_clr);
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writel(LRADC_CTRL0_ONCHIP_GROUNDREF, ®s->hw_lradc_ctrl0_clr);
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clrsetbits_le32(®s->hw_lradc_ctrl3,
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LRADC_CTRL3_CYCLE_TIME_MASK,
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LRADC_CTRL3_CYCLE_TIME_6MHZ);
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clrsetbits_le32(®s->hw_lradc_ctrl4,
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LRADC_CTRL4_LRADC7SELECT_MASK |
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LRADC_CTRL4_LRADC6SELECT_MASK,
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LRADC_CTRL4_LRADC7SELECT_CHANNEL7 |
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LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
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}
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void mxs_lradc_enable_batt_measurement(void)
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{
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struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
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debug("SPL: Enabling LRADC battery measurement\n");
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/* Check if the channel is present at all. */
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if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) {
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debug("SPL: LRADC channel 7 is not present - aborting\n");
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return;
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}
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debug("SPL: LRADC channel 7 is present - configuring\n");
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writel(LRADC_CTRL1_LRADC7_IRQ_EN, ®s->hw_lradc_ctrl1_clr);
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writel(LRADC_CTRL1_LRADC7_IRQ, ®s->hw_lradc_ctrl1_clr);
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clrsetbits_le32(®s->hw_lradc_conversion,
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LRADC_CONVERSION_SCALE_FACTOR_MASK,
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LRADC_CONVERSION_SCALE_FACTOR_LI_ION);
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writel(LRADC_CONVERSION_AUTOMATIC, ®s->hw_lradc_conversion_set);
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/* Configure the channel. */
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writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
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®s->hw_lradc_ctrl2_clr);
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writel(0xffffffff, ®s->hw_lradc_ch7_clr);
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clrbits_le32(®s->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK);
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writel(LRADC_CH_ACCUMULATE, ®s->hw_lradc_ch7_clr);
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/* Schedule the channel. */
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writel(1 << 7, ®s->hw_lradc_ctrl0_set);
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/* Start the channel sampling. */
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writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) |
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((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) |
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100, ®s->hw_lradc_delay3);
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writel(0xffffffff, ®s->hw_lradc_ch7_clr);
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writel(LRADC_DELAY_KICK, ®s->hw_lradc_delay3_set);
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debug("SPL: LRADC channel 7 configuration complete\n");
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}
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