mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-19 11:13:24 +09:00
752a0b085b
This is the initial import from Intel FSP release for Queensbay platform (Tunnel Creek processor and Topcliff Platform Controller Hub), which can be downloaded from Intel website. For more details, check http://www.intel.com/fsp. Note: U-Boot coding convention was applied to these codes, so it looks completely different from the original Intel release. Also update FSP support codes license header to use SPDX ID. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
59 lines
1.7 KiB
C
59 lines
1.7 KiB
C
/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* This file is automatically generated. Please do NOT modify !!!
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*
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* SPDX-License-Identifier: Intel
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*/
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#ifndef __VPDHEADER_H__
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#define __VPDHEADER_H__
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#pragma pack(1)
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struct upd_region_t {
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u64 sign; /* Offset 0x0000 */
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u64 reserved; /* Offset 0x0008 */
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u8 dummy[240]; /* Offset 0x0010 */
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u8 hda_verb_header[12]; /* Offset 0x0100 */
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u32 hda_verb_length; /* Offset 0x010C */
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u8 hda_verb_data0[16]; /* Offset 0x0110 */
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u8 hda_verb_data1[16]; /* Offset 0x0120 */
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u8 hda_verb_data2[16]; /* Offset 0x0130 */
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u8 hda_verb_data3[16]; /* Offset 0x0140 */
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u8 hda_verb_data4[16]; /* Offset 0x0150 */
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u8 hda_verb_data5[16]; /* Offset 0x0160 */
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u8 hda_verb_data6[16]; /* Offset 0x0170 */
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u8 hda_verb_data7[16]; /* Offset 0x0180 */
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u8 hda_verb_data8[16]; /* Offset 0x0190 */
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u8 hda_verb_data9[16]; /* Offset 0x01A0 */
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u8 hda_verb_data10[16]; /* Offset 0x01B0 */
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u8 hda_verb_data11[16]; /* Offset 0x01C0 */
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u8 hda_verb_data12[16]; /* Offset 0x01D0 */
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u8 hda_verb_data13[16]; /* Offset 0x01E0 */
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u8 hda_verb_pad[47]; /* Offset 0x01F0 */
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u16 terminator; /* Offset 0x021F */
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};
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#define VPD_IMAGE_ID 0x445056574F4E4E4D /* 'MNNOWVPD' */
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#define VPD_IMAGE_REV 0x00000301
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struct vpd_region_t {
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u64 sign; /* Offset 0x0000 */
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u32 img_rev; /* Offset 0x0008 */
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u32 upd_offset; /* Offset 0x000C */
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u8 unused[16]; /* Offset 0x0010 */
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u32 fsp_res_memlen; /* Offset 0x0020 */
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u8 disable_pcie1; /* Offset 0x0024 */
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u8 disable_pcie2; /* Offset 0x0025 */
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u8 disable_pcie3; /* Offset 0x0026 */
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u8 enable_azalia; /* Offset 0x0027 */
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u8 legacy_seg_decode; /* Offset 0x0028 */
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u8 pcie_port_ioh; /* Offset 0x0029 */
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};
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#pragma pack()
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#endif
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