mirror of
https://github.com/brain-hackers/u-boot-brain
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c59c085731
The command miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr) always returns 8 for the PHY address. It is the reset value for the PHY Address Register. Obviously, this default value could be incorrect. Moreover, as the PHY address is well known, there is no need to auto-detect it. Now, the PHY address must given as a parameter to the PHY initialization function. Additionally this patch also fixes some aesthetic issues. Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
127 lines
3.3 KiB
C
127 lines
3.3 KiB
C
/*
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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*
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* Based on Kirkwood support:
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include <asm/arch/gpio.h>
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#include "net2big_v2.h"
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#include "../common/common.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/* GPIO configuration */
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kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
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NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_SPI_SCn,
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MPP1_SPI_MOSI,
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MPP2_SPI_SCK,
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MPP3_SPI_MISO,
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MPP6_SYSRST_OUTn,
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MPP7_GPO, /* Request power-off */
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP13_GPIO, /* Rear power switch (on|auto) */
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MPP14_GPIO, /* USB fuse alarm */
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MPP15_GPIO, /* Rear power switch (auto|off) */
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MPP16_GPIO, /* SATA HDD1 power */
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MPP17_GPIO, /* SATA HDD2 power */
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MPP20_SATA1_ACTn,
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MPP21_SATA0_ACTn,
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MPP24_GPIO, /* USB mode select */
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MPP26_GPIO, /* USB device vbus */
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MPP28_GPIO, /* USB enable host vbus */
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MPP29_GPIO, /* GPIO extension ALE */
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MPP34_GPIO, /* Rear Push button 0=on 1=off */
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MPP35_GPIO, /* Inhibit switch power-off */
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MPP36_GPIO, /* SATA HDD1 presence */
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MPP37_GPIO, /* SATA HDD2 presence */
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MPP40_GPIO, /* eSATA presence */
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MPP44_GPIO, /* GPIO extension (data 0) */
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MPP45_GPIO, /* GPIO extension (data 1) */
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MPP46_GPIO, /* GPIO extension (data 2) */
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MPP47_GPIO, /* GPIO extension (addr 0) */
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MPP48_GPIO, /* GPIO extension (addr 1) */
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MPP49_GPIO, /* GPIO extension (addr 2) */
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/* Machine number */
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gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
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/* Boot parameters address */
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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return 0;
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}
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#if defined(CONFIG_MISC_INIT_R)
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int misc_init_r(void)
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{
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#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
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if (!getenv("ethaddr")) {
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uchar mac[6];
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if (lacie_read_mac_address(mac) == 0)
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eth_setenv_enetaddr("ethaddr", mac);
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}
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#endif
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return 0;
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}
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#endif
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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/* Configure and initialize PHY */
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void reset_phy(void)
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{
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mv_phy_88e1116_init("egiga0", 8);
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}
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#endif
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#if defined(CONFIG_KIRKWOOD_GPIO)
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/* Return GPIO push button status */
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static int
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do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
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}
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U_BOOT_CMD(button, 1, 1, do_read_push_button,
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"Return GPIO push button status 0=off 1=on", "");
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#endif
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