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https://github.com/brain-hackers/u-boot-brain
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285 lines
7.4 KiB
C
285 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <div64.h>
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#include <log.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/pcc.h>
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#include <asm/arch/sys_proto.h>
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#define PCC_CLKSRC_TYPES 2
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#define PCC_CLKSRC_NUM 7
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static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = {
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{ SCG_NIC1_BUS_CLK,
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SCG_NIC1_CLK,
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SCG_DDR_CLK,
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SCG_APLL_PFD2_CLK,
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SCG_APLL_PFD1_CLK,
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SCG_APLL_PFD0_CLK,
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USB_PLL_OUT,
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},
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{ SCG_SOSC_DIV2_CLK, /* SOSC BUS clock */
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MIPI_PLL_OUT,
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SCG_FIRC_DIV2_CLK, /* FIRC BUS clock */
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SCG_ROSC_CLK,
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SCG_NIC1_BUS_CLK,
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SCG_NIC1_CLK,
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SCG_APLL_PFD3_CLK,
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},
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};
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static struct pcc_entry pcc_arrays[] = {
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{PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
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{PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
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{PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
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{PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
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{PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
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};
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int pcc_clock_enable(enum pcc_clk clk, bool enable)
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{
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u32 reg, val;
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if (clk >= ARRAY_SIZE(pcc_arrays))
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return -EINVAL;
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reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
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val = readl(reg);
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clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n",
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clk, reg, val, enable);
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if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK))
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return -EPERM;
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if (enable)
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val |= PCC_CGC_MASK;
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else
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val &= ~PCC_CGC_MASK;
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writel(val, reg);
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clk_debug("pcc_clock_enable: val 0x%x\n", val);
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return 0;
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}
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/* The clock source select needs clock is disabled */
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int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src)
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{
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u32 reg, val, i, clksrc_type;
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if (clk >= ARRAY_SIZE(pcc_arrays))
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return -EINVAL;
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clksrc_type = pcc_arrays[clk].clksrc;
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if (clksrc_type >= CLKSRC_NO_PCS) {
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printf("No PCS field for the PCC %d, clksrc type %d\n",
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clk, clksrc_type);
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return -EPERM;
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}
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for (i = 0; i < PCC_CLKSRC_NUM; i++) {
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if (pcc_clksrc[clksrc_type][i] == src) {
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/* Find the clock src, then set it to PCS */
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break;
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}
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}
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if (i == PCC_CLKSRC_NUM) {
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printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
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return -EINVAL;
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}
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reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
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val = readl(reg);
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clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n",
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clk, reg, val, clksrc_type);
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if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
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(val & PCC_CGC_MASK)) {
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printf("Not permit to select clock source val = 0x%x\n", val);
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return -EPERM;
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}
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val &= ~PCC_PCS_MASK;
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val |= ((i + 1) << PCC_PCS_OFFSET);
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writel(val, reg);
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clk_debug("pcc_clock_sel: val 0x%x\n", val);
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return 0;
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}
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int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div)
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{
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u32 reg, val;
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if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 ||
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(div == 1 && frac != 0))
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return -EINVAL;
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if (pcc_arrays[clk].div >= PCC_NO_DIV) {
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printf("No DIV/FRAC field for the PCC %d\n", clk);
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return -EPERM;
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}
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reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
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val = readl(reg);
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if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
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(val & PCC_CGC_MASK)) {
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printf("Not permit to set div/frac val = 0x%x\n", val);
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return -EPERM;
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}
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if (frac)
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val |= PCC_FRAC_MASK;
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else
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val &= ~PCC_FRAC_MASK;
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val &= ~PCC_PCD_MASK;
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val |= (div - 1) & PCC_PCD_MASK;
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writel(val, reg);
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return 0;
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}
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bool pcc_clock_is_enable(enum pcc_clk clk)
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{
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u32 reg, val;
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if (clk >= ARRAY_SIZE(pcc_arrays))
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return -EINVAL;
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reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
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val = readl(reg);
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if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK))
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return true;
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return false;
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}
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int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)
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{
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u32 reg, val, clksrc_type;
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if (clk >= ARRAY_SIZE(pcc_arrays))
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return -EINVAL;
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clksrc_type = pcc_arrays[clk].clksrc;
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if (clksrc_type >= CLKSRC_NO_PCS) {
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printf("No PCS field for the PCC %d, clksrc type %d\n",
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clk, clksrc_type);
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return -EPERM;
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}
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reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
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val = readl(reg);
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clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n",
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clk, reg, val, clksrc_type);
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if (!(val & PCC_PR_MASK)) {
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printf("This pcc slot is not present = 0x%x\n", val);
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return -EPERM;
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}
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val &= PCC_PCS_MASK;
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val = (val >> PCC_PCS_OFFSET);
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if (!val) {
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printf("Clock source is off\n");
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return -EIO;
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}
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*src = pcc_clksrc[clksrc_type][val - 1];
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clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src);
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return 0;
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}
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u32 pcc_clock_get_rate(enum pcc_clk clk)
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{
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u32 reg, val, rate, frac, div;
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enum scg_clk parent;
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int ret;
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ret = pcc_clock_get_clksrc(clk, &parent);
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if (ret)
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return 0;
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rate = scg_clk_get_rate(parent);
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clk_debug("pcc_clock_get_rate: parent rate %u\n", rate);
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if (pcc_arrays[clk].div == PCC_HAS_DIV) {
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reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
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val = readl(reg);
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frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
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div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET;
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/*
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* Theoretically don't have overflow in the calc,
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* the rate won't exceed 2G
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*/
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rate = rate * (frac + 1) / (div + 1);
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}
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clk_debug("pcc_clock_get_rate: rate %u\n", rate);
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return rate;
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}
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