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![Graeme Russ](/assets/img/avatar_default.png)
Moved ali512x.h from include/asm-i386/ic/ to /include Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
638 lines
16 KiB
C
638 lines
16 KiB
C
/*
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/ic/sc520.h>
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#include <ali512x.h>
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#include <spi.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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#undef SC520_CDP_DEBUG
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#ifdef SC520_CDP_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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/* ------------------------------------------------------------------------- */
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/*
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* Theory:
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* We first set up all IRQs to be non-pci, edge triggered,
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* when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
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* called we reallocate irqs to the pci bus with sc520_pci_set_irq()
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* as needed. Whe choose the irqs to gram from a configurable list
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* inside pci_sc520_fixup_irq() (If this list contains stupid irq's
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* such as 0 thngas will not work)
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*/
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static void irq_init(void)
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{
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/* disable global interrupt mode */
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write_mmcr_byte(SC520_PICICR, 0x40);
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/* set all irqs to edge */
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write_mmcr_byte(SC520_MPICMODE, 0x00);
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write_mmcr_byte(SC520_SL1PICMODE, 0x00);
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write_mmcr_byte(SC520_SL2PICMODE, 0x00);
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/* active low polarity on PIC interrupt pins,
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* active high polarity on all other irq pins */
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write_mmcr_word(SC520_INTPINPOL, 0x0000);
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/* set irq number mapping */
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write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */
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write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */
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write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */
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write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */
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write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */
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write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */
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write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */
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write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */
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write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */
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write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */
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write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
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write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */
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write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */
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write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */
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write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */
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write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */
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write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */
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if (CONFIG_SYS_USE_SIO_UART) {
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write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
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write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
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write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
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write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
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} else {
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write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */
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write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */
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write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */
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write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ4 (ISA IRQ4) */
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}
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write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
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write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
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write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
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write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
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write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
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write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9); /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
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write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
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write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
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write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
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write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */
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write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */
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}
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#ifdef CONFIG_PCI
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/* PCI stuff */
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static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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/* a configurable lists of irqs to steal
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* when we need one (a board with more pci interrupt pins
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* would use a larger table */
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static int irq_list[] = {
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CONFIG_SYS_FIRST_PCI_IRQ,
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CONFIG_SYS_SECOND_PCI_IRQ,
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CONFIG_SYS_THIRD_PCI_IRQ,
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CONFIG_SYS_FORTH_PCI_IRQ
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};
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static int next_irq_index=0;
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uchar tmp_pin;
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int pin;
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pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
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pin = tmp_pin;
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pin-=1; /* pci config space use 1-based numbering */
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if (-1 == pin) {
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return; /* device use no irq */
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}
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/* map device number + pin to a pin on the sc520 */
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switch (PCI_DEV(dev)) {
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case 20:
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pin+=SC520_PCI_INTA;
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break;
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case 19:
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pin+=SC520_PCI_INTB;
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break;
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case 18:
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pin+=SC520_PCI_INTC;
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break;
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case 17:
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pin+=SC520_PCI_INTD;
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break;
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default:
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return;
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}
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pin&=3; /* wrap around */
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if (sc520_pci_ints[pin] == -1) {
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/* re-route one interrupt for us */
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if (next_irq_index > 3) {
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return;
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}
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if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
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return;
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}
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next_irq_index++;
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}
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if (-1 != sc520_pci_ints[pin]) {
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
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sc520_pci_ints[pin]);
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}
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PRINTF("fixup_irq: device %d pin %c irq %d\n",
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PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
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}
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static struct pci_controller sc520_cdp_hose = {
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fixup_irq: pci_sc520_cdp_fixup_irq,
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};
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void pci_init_board(void)
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{
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pci_sc520_init(&sc520_cdp_hose);
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}
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#endif
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static void silence_uart(int port)
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{
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outb(0, port+1);
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}
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void setup_ali_sio(int uart_primary)
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{
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ali512x_init();
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ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0);
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ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3);
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ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4);
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ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3);
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ali512x_set_rtc(ALI_DISABLED, 0, 0);
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ali512x_set_kbc(ALI_ENABLED, 1, 12);
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ali512x_set_cio(ALI_ENABLED);
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/* IrDa pins */
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ali512x_cio_function(12, 1, 0, 0);
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ali512x_cio_function(13, 1, 0, 0);
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/* SSI chip select pins */
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ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */
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ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */
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ali512x_cio_function(16, 0, 0, 0); /* SSI_SPI# */
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/* Board REV pins */
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ali512x_cio_function(20, 0, 0, 1);
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ali512x_cio_function(21, 0, 0, 1);
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ali512x_cio_function(22, 0, 0, 1);
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ali512x_cio_function(23, 0, 0, 1);
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}
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/* set up the ISA bus timing and system address mappings */
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static void bus_init(void)
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{
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/* set up the GP IO pins */
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write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */
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write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */
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write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */
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write_mmcr_byte(SC520_CLKSEL, 0x70);
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write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */
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write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */
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write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */
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write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */
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write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */
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write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */
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write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */
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write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */
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write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */
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write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */
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/* adjust the memory map:
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* by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
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* and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
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* we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
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/* SRAM = GPCS3 128k @ d0000-effff*/
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write_mmcr_long(SC520_PAR2, 0x4e00400d);
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/* IDE0 = GPCS6 1f0-1f7 */
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write_mmcr_long(SC520_PAR3, 0x380801f0);
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/* IDE1 = GPCS7 3f6 */
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write_mmcr_long(SC520_PAR4, 0x3c0003f6);
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/* bootcs */
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write_mmcr_long(SC520_PAR12, 0x8bffe800);
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/* romcs2 */
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write_mmcr_long(SC520_PAR13, 0xcbfff000);
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/* romcs1 */
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write_mmcr_long(SC520_PAR14, 0xabfff800);
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/* 680 LEDS */
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write_mmcr_long(SC520_PAR15, 0x30000640);
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write_mmcr_byte(SC520_ADDDECCTL, 0);
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asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
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if (CONFIG_SYS_USE_SIO_UART) {
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write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
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setup_ali_sio(1);
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} else {
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write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
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setup_ali_sio(0);
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silence_uart(0x3e8);
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silence_uart(0x2e8);
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}
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}
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/* GPCS usage
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* GPCS0 PIO27 (NMI)
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* GPCS1 ROMCS1
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* GPCS2 ROMCS2
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* GPCS3 SRAMCS PAR2
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* GPCS4 unused PAR3
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* GPCS5 unused PAR4
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* GPCS6 IDE
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* GPCS7 IDE
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*/
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/* par usage:
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* PAR0 legacy_video
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* PAR1 PCI ROM mapping
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* PAR2 SRAM
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* PAR3 IDE
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* PAR4 IDE
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* PAR5 legacy_video
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* PAR6 legacy_video
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* PAR7 legacy_video
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* PAR8 legacy_video
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* PAR9 legacy_video
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* PAR10 legacy_video
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* PAR11 ISAROM
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* PAR12 BOOTCS
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* PAR13 ROMCS1
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* PAR14 ROMCS2
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* PAR15 Port 0x680 LED display
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*/
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/*
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* This function should map a chunk of size bytes
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* of the system address space to the ISA bus
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*
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* The function will return the memory address
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* as seen by the host (which may very will be the
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* same as the bus address)
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*/
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u32 isa_map_rom(u32 bus_addr, int size)
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{
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u32 par;
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PRINTF("isa_map_rom asked to map %d bytes at %x\n",
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size, bus_addr);
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par = size;
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if (par < 0x80000) {
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par = 0x80000;
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}
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par >>= 12;
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par--;
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par&=0x7f;
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par <<= 18;
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par |= (bus_addr>>12);
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par |= 0x50000000;
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PRINTF ("setting PAR11 to %x\n", par);
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/* Map rom 0x10000 with PAR1 */
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write_mmcr_long(SC520_PAR11, par);
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return bus_addr;
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}
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/*
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* this function removed any mapping created
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* with pci_get_rom_window()
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*/
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void isa_unmap_rom(u32 addr)
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{
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PRINTF("isa_unmap_rom asked to unmap %x", addr);
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if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
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write_mmcr_long(SC520_PAR11, 0);
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PRINTF(" done\n");
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return;
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}
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PRINTF(" not ours\n");
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}
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#ifdef CONFIG_PCI
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#define PCI_ROM_TEMP_SPACE 0x10000
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/*
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* This function should map a chunk of size bytes
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* of the system address space to the PCI bus,
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* suitable to map PCI ROMS (bus address < 16M)
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* the function will return the host memory address
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* which should be converted into a bus address
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* before used to configure the PCI rom address
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* decoder
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*/
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u32 pci_get_rom_window(struct pci_controller *hose, int size)
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{
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u32 par;
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par = size;
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if (par < 0x80000) {
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par = 0x80000;
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}
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par >>= 16;
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par--;
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par&=0x7ff;
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par <<= 14;
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par |= (PCI_ROM_TEMP_SPACE>>16);
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par |= 0x72000000;
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PRINTF ("setting PAR1 to %x\n", par);
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/* Map rom 0x10000 with PAR1 */
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write_mmcr_long(SC520_PAR1, par);
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return PCI_ROM_TEMP_SPACE;
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}
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/*
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* this function removed any mapping created
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* with pci_get_rom_window()
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*/
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void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
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{
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PRINTF("pci_remove_rom_window: %x", addr);
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if (addr == PCI_ROM_TEMP_SPACE) {
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write_mmcr_long(SC520_PAR1, 0);
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PRINTF(" done\n");
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return;
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}
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PRINTF(" not ours\n");
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}
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/*
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* This function is called in order to provide acces to the
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* legacy video I/O ports on the PCI bus.
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* After this function accesses to I/O ports 0x3b0-0x3bb and
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* 0x3c0-0x3df shuld result in transactions on the PCI bus.
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*
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*/
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int pci_enable_legacy_video_ports(struct pci_controller *hose)
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{
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/* Map video memory to 0xa0000*/
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write_mmcr_long(SC520_PAR0, 0x7200400a);
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/* forward all I/O accesses to PCI */
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write_mmcr_byte(SC520_ADDDECCTL,
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read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
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/* so we map away all io ports to pci (only way to access pci io
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* below 0x400. But then we have to map back the portions that we dont
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* use so that the generate cycles on the GPIO bus where the sio and
|
|
* ISA slots are connected, this requre the use of several PAR registers
|
|
*/
|
|
|
|
/* bring 0x100 - 0x1ef back to ISA using PAR5 */
|
|
write_mmcr_long(SC520_PAR5, 0x30ef0100);
|
|
|
|
/* IDE use 1f0-1f7 */
|
|
|
|
/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
|
|
write_mmcr_long(SC520_PAR6, 0x30ff01f8);
|
|
|
|
/* com2 use 2f8-2ff */
|
|
|
|
/* bring 0x300 - 0x3af back to ISA using PAR7 */
|
|
write_mmcr_long(SC520_PAR7, 0x30af0300);
|
|
|
|
/* vga use 3b0-3bb */
|
|
|
|
/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
|
|
write_mmcr_long(SC520_PAR8, 0x300303bc);
|
|
|
|
/* vga use 3c0-3df */
|
|
|
|
/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
|
|
write_mmcr_long(SC520_PAR9, 0x301503e0);
|
|
|
|
/* ide use 3f6 */
|
|
|
|
/* bring 0x3f7 back to ISA using PAR10 */
|
|
write_mmcr_long(SC520_PAR10, 0x300003f7);
|
|
|
|
/* com1 use 3f8-3ff */
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Miscelaneous platform dependent initialisations
|
|
*/
|
|
|
|
int board_init(void)
|
|
{
|
|
init_sc520();
|
|
bus_init();
|
|
irq_init();
|
|
|
|
/* max drive current on SDRAM */
|
|
write_mmcr_word(SC520_DSCTL, 0x0100);
|
|
|
|
/* enter debug mode after next reset (only if jumper is also set) */
|
|
write_mmcr_byte(SC520_RESCFG, 0x08);
|
|
/* configure the software timer to 33.333MHz */
|
|
write_mmcr_byte(SC520_SWTMRCFG, 0);
|
|
gd->bus_clk = 33333000;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
init_sc520_dram();
|
|
return 0;
|
|
}
|
|
|
|
void show_boot_progress(int val)
|
|
{
|
|
if (val < -32) val = -1; /* let things compatible */
|
|
outb(val&0xff, 0x80);
|
|
outb((val&0xff00)>>8, 0x680);
|
|
}
|
|
|
|
|
|
int last_stage_init(void)
|
|
{
|
|
int minor;
|
|
int major;
|
|
|
|
major = minor = 0;
|
|
major |= ali512x_cio_in(23)?2:0;
|
|
major |= ali512x_cio_in(22)?1:0;
|
|
minor |= ali512x_cio_in(21)?2:0;
|
|
minor |= ali512x_cio_in(20)?1:0;
|
|
|
|
printf("AMD SC520 CDP revision %d.%d\n", major, minor);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
void ssi_chip_select(int dev)
|
|
{
|
|
|
|
/* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
|
|
switch (dev) {
|
|
case 1: /* SPI EEPROM */
|
|
ali512x_cio_out(16, 0);
|
|
break;
|
|
|
|
case 2: /* MW EEPROM */
|
|
ali512x_cio_out(15, 1);
|
|
break;
|
|
|
|
case 3: /* AUX */
|
|
ali512x_cio_out(14, 1);
|
|
break;
|
|
|
|
case 0:
|
|
ali512x_cio_out(16, 1);
|
|
ali512x_cio_out(15, 0);
|
|
ali512x_cio_out(14, 0);
|
|
break;
|
|
|
|
default:
|
|
printf("Illegal SSI device requested: %d\n", dev);
|
|
}
|
|
}
|
|
|
|
void spi_eeprom_probe(int x)
|
|
{
|
|
}
|
|
|
|
int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void spi_init_f(void)
|
|
{
|
|
#ifdef CONFIG_SYS_SC520_CDP_USE_SPI
|
|
spi_eeprom_probe(1);
|
|
#endif
|
|
#ifdef CONFIG_SYS_SC520_CDP_USE_MW
|
|
mw_eeprom_probe(2);
|
|
#endif
|
|
}
|
|
|
|
ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
|
|
{
|
|
int offset;
|
|
int i;
|
|
ssize_t res;
|
|
|
|
offset = 0;
|
|
for (i=0;i<alen;i++) {
|
|
offset <<= 8;
|
|
offset |= addr[i];
|
|
}
|
|
|
|
#ifdef CONFIG_SYS_SC520_CDP_USE_SPI
|
|
res = spi_eeprom_read(1, offset, buffer, len);
|
|
#endif
|
|
#ifdef CONFIG_SYS_SC520_CDP_USE_MW
|
|
res = mw_eeprom_read(2, offset, buffer, len);
|
|
#endif
|
|
#if !defined(CONFIG_SYS_SC520_CDP_USE_SPI) && !defined(CONFIG_SYS_SC520_CDP_USE_MW)
|
|
res = 0;
|
|
#endif
|
|
return res;
|
|
}
|
|
|
|
ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
|
|
{
|
|
int offset;
|
|
int i;
|
|
ssize_t res;
|
|
|
|
offset = 0;
|
|
for (i=0;i<alen;i++) {
|
|
offset <<= 8;
|
|
offset |= addr[i];
|
|
}
|
|
|
|
#ifdef CONFIG_SYS_SC520_CDP_USE_SPI
|
|
res = spi_eeprom_write(1, offset, buffer, len);
|
|
#endif
|
|
#ifdef CONFIG_SYS_SC520_CDP_USE_MW
|
|
res = mw_eeprom_write(2, offset, buffer, len);
|
|
#endif
|
|
#if !defined(CONFIG_SYS_SC520_CDP_USE_SPI) && !defined(CONFIG_SYS_SC520_CDP_USE_MW)
|
|
res = 0;
|
|
#endif
|
|
return res;
|
|
}
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
return pci_eth_init(bis);
|
|
}
|