mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
74e56d1953
With MRC cache enabled, when typing 'reset' in the U-Boot shell, BayTrail FSP initialization hangs at "Configuring Memory Start": Setting BootMode to 0 Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE About to call MrcInit(); BayleyBay Platform Type CurrentMrcData.BootMode = 4 Taking Fastboot path! Configuring Memory Start... Changing reset_cpu() to do a full system reset fixes this issue. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
74 lines
1.2 KiB
C
74 lines
1.2 KiB
C
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mmc.h>
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#include <pci_ids.h>
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#include <asm/irq.h>
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#include <asm/mrccache.h>
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#include <asm/post.h>
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static struct pci_device_id mmc_supported[] = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
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};
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int cpu_mmc_init(bd_t *bis)
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{
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return pci_mmc_init("ValleyView SDHCI", mmc_supported,
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ARRAY_SIZE(mmc_supported));
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}
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#ifndef CONFIG_EFI_APP
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int arch_cpu_init(void)
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{
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int ret;
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post_code(POST_CPU_INIT);
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#ifdef CONFIG_SYS_X86_TSC_TIMER
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timer_set_base(rdtsc());
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#endif
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ret = x86_cpu_init_f();
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if (ret)
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return ret;
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return 0;
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}
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int arch_misc_init(void)
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{
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if (!ll_boot_init())
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return 0;
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#ifdef CONFIG_ENABLE_MRC_CACHE
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/*
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* We intend not to check any return value here, as even MRC cache
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* is not saved successfully, it is not a severe error that will
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* prevent system from continuing to boot.
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*/
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mrccache_save();
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#endif
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return pirq_init();
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}
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int reserve_arch(void)
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{
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#ifdef CONFIG_ENABLE_MRC_CACHE
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return mrccache_reserve();
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#else
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return 0;
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#endif
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}
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#endif
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void reset_cpu(ulong addr)
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{
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/* cold reset */
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x86_full_reset();
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}
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