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https://github.com/brain-hackers/u-boot-brain
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![Mike Frysinger](/assets/img/avatar_default.png)
The environment is the canonical storage location of the mac address, so we're killing off the global data location and moving everything to querying the env directly. Rather than have common ppc code call a board-specific function like load_sernum_ethaddr(), have each board call it in its own board-specific misc_init_r() function. The boards that get converted here are: - kup4k/kup4x - pcs440ep - tqm8xx Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com> CC: Stefan Roese <sr@denx.de>
405 lines
11 KiB
C
405 lines
11 KiB
C
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include "../common/kup.h"
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#ifdef CONFIG_KUP4K_LOGO
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#include "s1d13706.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#undef DEBUG
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#ifdef DEBUG
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# define debugk(fmt,args...) printf(fmt ,##args)
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#else
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# define debugk(fmt,args...)
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#endif
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typedef struct {
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volatile unsigned char *VmemAddr;
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volatile unsigned char *RegAddr;
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} FB_INFO_S1D13xxx;
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_KUP4K_LOGO
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void lcd_logo(bd_t *bd);
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#endif
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
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0x1FF77C47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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uchar *latch,rev,mod;
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/*
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* Init ChipSelect #4 (CAN + HW-Latch)
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*/
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immap->im_memctl.memc_or4 = 0xFFFF8926;
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immap->im_memctl.memc_br4 = 0x90000401;
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__asm__ ("eieio");
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latch=(uchar *)0x90000200;
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rev = (*latch & 0xF8) >> 3;
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mod=(*latch & 0x03);
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printf ("Board: KUP4K Rev %d.%d\n",rev,mod);
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size_b0 = 0;
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long int size_b1 = 0;
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long int size_b2 = 0;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */
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/* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */
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/* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */
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/* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */
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memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
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udelay (1);
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memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
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udelay (1);
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memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
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udelay (1);
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
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udelay (1);
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memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
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udelay (1);
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memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
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udelay (1);
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memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
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udelay (1);
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memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
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udelay (1);
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memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
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udelay (1);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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#if 0 /* 3 x 8MB */
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size_b0 = 0x00800000;
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size_b1 = 0x00800000;
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size_b2 = 0x00800000;
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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udelay (1000);
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memctl->memc_or1 = 0xFF800A00;
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memctl->memc_br1 = 0x00000081;
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memctl->memc_or2 = 0xFF000A00;
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memctl->memc_br2 = 0x00800081;
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memctl->memc_or3 = 0xFE000A00;
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memctl->memc_br3 = 0x01000081;
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#else /* 3 x 16 MB */
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size_b0 = 0x01000000;
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size_b1 = 0x01000000;
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size_b2 = 0x01000000;
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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udelay (1000);
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memctl->memc_or1 = 0xFF000A00;
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memctl->memc_br1 = 0x00000081;
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memctl->memc_or2 = 0xFE000A00;
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memctl->memc_br2 = 0x01000081;
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memctl->memc_or3 = 0xFC000A00;
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memctl->memc_br3 = 0x02000081;
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#endif
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udelay (10000);
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return (size_b0 + size_b1 + size_b2);
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}
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/* ------------------------------------------------------------------------- */
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int misc_init_r (void)
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{
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#ifdef CONFIG_STATUS_LED
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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#endif
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#ifdef CONFIG_KUP4K_LOGO
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bd_t *bd = gd->bd;
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lcd_logo (bd);
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#endif /* CONFIG_KUP4K_LOGO */
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#ifdef CONFIG_IDE_LED
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/* Configure PA8 as output port */
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immap->im_ioport.iop_padir |= 0x80;
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immap->im_ioport.iop_paodr |= 0x80;
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immap->im_ioport.iop_papar &= ~0x80;
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immap->im_ioport.iop_padat |= 0x80; /* turn it off */
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#endif
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load_sernum_ethaddr();
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setenv("hw","4k");
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poweron_key();
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return (0);
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}
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#ifdef CONFIG_KUP4K_LOGO
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void lcd_logo (bd_t * bd)
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{
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FB_INFO_S1D13xxx fb_info;
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S1D_INDEX s1dReg;
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S1D_VALUE s1dValue;
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl;
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ushort i;
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uchar *fb;
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int rs, gs, bs;
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int r = 8, g = 8, b = 4;
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int r1, g1, b1;
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int n;
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char tmp[64]; /* long enough for environment variables */
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int tft = 0;
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immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
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immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM);
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immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */
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immr->im_cpm.cp_pbdir |= (PB_LCD_PWM);
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/*----------------------------------------------------------------------------- */
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/* Initialize the chip and the frame buffer driver. */
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/*----------------------------------------------------------------------------- */
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memctl = &immr->im_memctl;
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/*
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* Init ChipSelect #5 (S1D13768)
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*/
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memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */
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memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
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__asm__ ("eieio");
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fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
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fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
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if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
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|| (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
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printf ("Warning:LCD Controller S1D13706 not found\n");
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setenv ("lcd", "none");
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return;
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}
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for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) {
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s1dReg = aS1DRegs_prelimn[i].Index;
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s1dValue = aS1DRegs_prelimn[i].Value;
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debugk ("s13768 reg: %02x value: %02x\n",
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aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value);
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((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
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s1dValue;
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}
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n = getenv_r ("lcd", tmp, sizeof (tmp));
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if (n > 0) {
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if (!strcmp ("tft", tmp))
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tft = 1;
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else
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tft = 0;
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}
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#if 0
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if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04)
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tft = 0;
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else
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tft = 1;
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#endif
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debugk ("Port=0x%02x -> TFT=%d\n", tft,
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((S1D_VALUE *) fb_info.RegAddr)[0xAC]);
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/* init controller */
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if (!tft) {
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for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) {
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s1dReg = aS1DRegs_stn[i].Index;
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s1dValue = aS1DRegs_stn[i].Value;
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debugk ("s13768 reg: %02x value: %02x\n",
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aS1DRegs_stn[i].Index,
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aS1DRegs_stn[i].Value);
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((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] =
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s1dValue;
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}
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n = getenv_r ("contrast", tmp, sizeof (tmp));
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((S1D_VALUE *) fb_info.RegAddr)[0xB3] =
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(n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0;
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switch (bd->bi_busfreq) {
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case 40000000:
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((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
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((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
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break;
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case 48000000:
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((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
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((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
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break;
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default:
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printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
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case 64000000:
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((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
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((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
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break;
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}
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/* setenv("lcd","stn"); */
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} else {
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for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) {
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s1dReg = aS1DRegs_tft[i].Index;
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s1dValue = aS1DRegs_tft[i].Value;
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debugk ("s13768 reg: %02x value: %02x\n",
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aS1DRegs_tft[i].Index,
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aS1DRegs_tft[i].Value);
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((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
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s1dValue;
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}
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switch (bd->bi_busfreq) {
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default:
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printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
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case 40000000:
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((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42;
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((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30;
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break;
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}
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/* setenv("lcd","tft"); */
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}
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/* create and set colormap */
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rs = 256 / (r - 1);
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gs = 256 / (g - 1);
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bs = 256 / (b - 1);
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for (i = 0; i < 256; i++) {
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r1 = (rs * ((i / (g * b)) % r)) * 255;
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g1 = (gs * ((i / b) % g)) * 255;
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b1 = (bs * ((i) % b)) * 255;
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debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4);
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S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
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(b1 >> 4));
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}
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/* copy bitmap */
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fb = (uchar *) (fb_info.VmemAddr);
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memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
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}
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#endif /* CONFIG_KUP4K_LOGO */
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