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74749f1e84
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
40 lines
848 B
Plaintext
40 lines
848 B
Plaintext
* Intel Apollo Lake pin controller
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The Apollo Lake (APL) pin controller is used to select the function of a pin
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and to configure it.
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Required properties:
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- compatible: "intel,apl-pinctrl"
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- intel,p2sb-port-id: Port ID number within the parent P2SB
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- reg: PCI address of the controller
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices.
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Optional subnodes:
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GPIO nodes may be added as children of the pinctrl nodes. See intel,apl-gpio
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for the binding.
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Example:
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...
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{
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p2sb: p2sb@d,0 {
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reg = <0x02006810 0 0 0 0>;
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compatible = "intel,apl-p2sb";
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early-regs = <IOMAP_P2SB_BAR 0x100000>;
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n {
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compatible = "intel,apl-pinctrl";
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intel,p2sb-port-id = <PID_GPIO_N>;
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gpio_n: gpio-n {
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compatible = "intel,apl-gpio";
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#gpio-cells = <2>;
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};
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};
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};
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};
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...
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