mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
74631b69d6
Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Because the limitation of internal SRAM size, the SPL with driver model can't be supported, disable the SPL option. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
226 lines
6.1 KiB
C
226 lines
6.1 KiB
C
/*
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* Copyright (C) 2012 Atmel Corporation
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*
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* Configuation settings for the AT91SAM9X5EK board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H__
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#define __CONFIG_H__
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#include <asm/hardware.h>
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#define CONFIG_SYS_TEXT_BASE 0x26f00000
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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#define CONFIG_AT91SAM9X5EK
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* general purpose I/O */
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#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
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/* LCD */
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#define LCD_BPP LCD_COLOR16
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#define LCD_OUTPUT_BPP 24
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#define CONFIG_LCD_LOGO
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#define CONFIG_LCD_INFO
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#define CONFIG_LCD_INFO_BELOW_LOGO
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#define CONFIG_ATMEL_HLCD
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#define CONFIG_ATMEL_LCD_RGB565
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_NAND
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/*
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* define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
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* NB: in this case, USB 1.1 devices won't be recognized.
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*/
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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/* DataFlash */
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#ifdef CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#endif
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC 1
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#define CONFIG_ATMEL_NAND_HW_PMECC 1
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#define CONFIG_PMECC_CAP 2
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#define CONFIG_PMECC_SECTOR_SIZE 512
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#define CONFIG_CMD_NAND_TRIMFFS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_RBTREE
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#define CONFIG_LZO
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#define CONFIG_CMD_UBIFS
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#endif
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/* USB */
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#ifdef CONFIG_CMD_USB
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#ifndef CONFIG_USB_EHCI
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
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#endif
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x26e00000
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#ifdef CONFIG_SYS_USE_NANDFLASH
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/* bootstrap + u-boot + env + linux in nandflash */
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET 0x120000
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#define CONFIG_ENV_OFFSET_REDUND 0x100000
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#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
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#define CONFIG_BOOTCOMMAND "nand read " \
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"0x22000000 0x200000 0x300000; " \
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"bootm 0x22000000"
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#elif defined(CONFIG_SYS_USE_SPIFLASH)
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/* bootstrap + u-boot + env + linux in spi flash */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x5000
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#define CONFIG_ENV_SIZE 0x3000
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#define CONFIG_ENV_SECT_SIZE 0x1000
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_BOOTCOMMAND "sf probe 0; " \
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"sf read 0x22000000 0x100000 0x300000; " \
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"bootm 0x22000000"
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#elif defined(CONFIG_SYS_USE_DATAFLASH)
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/* bootstrap + u-boot + env + linux in data flash */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x4200
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#define CONFIG_ENV_SIZE 0x4200
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#define CONFIG_ENV_SECT_SIZE 0x210
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_BOOTCOMMAND "sf probe 0; " \
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"sf read 0x22000000 0x84000 0x294000; " \
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"bootm 0x22000000"
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#else /* CONFIG_SYS_USE_MMC */
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/* bootstrap + u-boot + env + linux in mmc */
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#define CONFIG_ENV_IS_IN_FAT
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#define CONFIG_FAT_WRITE
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#define FAT_ENV_INTERFACE "mmc"
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#define FAT_ENV_FILE "uboot.env"
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#define FAT_ENV_DEVICE_AND_PART "0"
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#define CONFIG_ENV_SIZE 0x4000
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#endif
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#ifdef CONFIG_SYS_USE_MMC
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#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \
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"mtdparts=atmel_nand:" \
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"8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
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"root=/dev/mmcblk0p2 " \
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"rw rootfstype=ext4 rootwait"
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#else
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#define CONFIG_BOOTARGS \
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"console=ttyS0,115200 earlyprintk " \
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"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
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"256k(env),256k(env_redundant),256k(spare)," \
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"512k(dtb),6M(kernel)ro,-(rootfs) " \
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"rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
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#endif
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
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/* SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE 0x6000
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#define CONFIG_SPL_STACK 0x308000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#define CONFIG_SYS_MASTER_CLOCK 132096000
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#define CONFIG_SYS_AT91_PLLA 0x20c73f03
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#ifdef CONFIG_SYS_USE_MMC
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#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#elif CONFIG_SYS_USE_NANDFLASH
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
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#elif CONFIG_SYS_USE_SPIFLASH
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
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#endif
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#endif
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