mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
429 lines
9.1 KiB
ArmAsm
429 lines
9.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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#include <linux/linkage.h>
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.section ".text.init", "x"
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.macro init_arm_erratum
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/* ARM erratum ID #468414 */
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mrc 15, 0, r1, c1, c0, 1
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orr r1, r1, #(1 << 5) /* enable L1NEON bit */
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mcr 15, 0, r1, c1, c0, 1
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.endm
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/*
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* L2CC Cache setup/invalidation/disable
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*/
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.macro init_l2cc
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/* explicitly disable L2 cache */
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mrc 15, 0, r0, c1, c0, 1
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bic r0, r0, #0x2
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mcr 15, 0, r0, c1, c0, 1
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/* reconfigure L2 cache aux control reg */
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ldr r0, =0xC0 | /* tag RAM */ \
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0x4 | /* data RAM */ \
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1 << 24 | /* disable write allocate delay */ \
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1 << 23 | /* disable write allocate combine */ \
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1 << 22 /* disable write allocate */
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#if defined(CONFIG_MX51)
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ldr r3, [r4, #ROM_SI_REV]
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cmp r3, #0x10
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/* disable write combine for TO 2 and lower revs */
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orrls r0, r0, #1 << 25
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#endif
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mcr 15, 1, r0, c9, c0, 2
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/* enable L2 cache */
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mrc 15, 0, r0, c1, c0, 1
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orr r0, r0, #2
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mcr 15, 0, r0, c1, c0, 1
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.endm /* init_l2cc */
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/* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.*/
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.macro init_aips
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =0x77777777
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str r1, [r0, #0x0]
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str r1, [r0, #0x4]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x0]
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str r1, [r0, #0x4]
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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.endm /* init_aips */
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/* M4IF setup */
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.macro init_m4if
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#ifdef CONFIG_MX51
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/* VPU and IPU given higher priority (0x4)
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* IPU accesses with ID=0x1 given highest priority (=0xA)
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*/
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ldr r0, =M4IF_BASE_ADDR
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ldr r1, =0x00000203
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str r1, [r0, #0x40]
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str r4, [r0, #0x44]
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ldr r1, =0x00120125
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str r1, [r0, #0x9C]
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ldr r1, =0x001901A3
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str r1, [r0, #0x48]
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#endif
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.endm /* init_m4if */
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.macro setup_pll pll, freq
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ldr r0, =\pll
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adr r2, W_DP_\freq
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bl setup_pll_func
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.endm
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#define W_DP_OP 0
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#define W_DP_MFD 4
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#define W_DP_MFN 8
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setup_pll_func:
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ldr r1, =0x00001232
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str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
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mov r1, #0x2
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str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
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ldr r1, [r2, #W_DP_OP]
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str r1, [r0, #PLL_DP_OP]
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str r1, [r0, #PLL_DP_HFS_OP]
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ldr r1, [r2, #W_DP_MFD]
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str r1, [r0, #PLL_DP_MFD]
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str r1, [r0, #PLL_DP_HFS_MFD]
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ldr r1, [r2, #W_DP_MFN]
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str r1, [r0, #PLL_DP_MFN]
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str r1, [r0, #PLL_DP_HFS_MFN]
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ldr r1, =0x00001232
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str r1, [r0, #PLL_DP_CTL]
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1: ldr r1, [r0, #PLL_DP_CTL]
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ands r1, r1, #0x1
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beq 1b
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/* r10 saved upper lr */
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mov pc, lr
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.macro setup_pll_errata pll, freq
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ldr r2, =\pll
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str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
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ldr r1, =0x00001236
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str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
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1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
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ands r1, r1, #0x1
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beq 1b
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ldr r5, \freq
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str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
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str r5, [r2, #PLL_DP_HFS_MFN]
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mov r1, #0x1
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str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
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2: ldr r1, [r2, #PLL_DP_CONFIG]
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tst r1, #1
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bne 2b
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ldr r1, =100 /* Wait at least 4 us */
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3: subs r1, r1, #1
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bge 3b
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mov r1, #0x2
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str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
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.endm
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.macro init_clock
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#if defined (CONFIG_MX51)
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ldr r0, =CCM_BASE_ADDR
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/* Gate of clocks to the peripherals first */
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ldr r1, =0x3FFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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str r4, [r0, #CLKCTL_CCGR1]
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str r4, [r0, #CLKCTL_CCGR2]
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str r4, [r0, #CLKCTL_CCGR3]
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ldr r1, =0x00030000
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str r1, [r0, #CLKCTL_CCGR4]
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ldr r1, =0x00FFF030
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str r1, [r0, #CLKCTL_CCGR5]
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ldr r1, =0x00000300
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str r1, [r0, #CLKCTL_CCGR6]
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/* Disable IPU and HSC dividers */
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mov r1, #0x60000
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str r1, [r0, #CLKCTL_CCDR]
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/* Make sure to switch the DDR away from PLL 1 */
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ldr r1, =0x19239145
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str r1, [r0, #CLKCTL_CBCDR]
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/* make sure divider effective */
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1: ldr r1, [r0, #CLKCTL_CDHIPR]
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cmp r1, #0x0
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bne 1b
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/* Switch ARM to step clock */
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mov r1, #0x4
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str r1, [r0, #CLKCTL_CCSR]
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#if defined(CONFIG_MX51_PLL_ERRATA)
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setup_pll PLL1_BASE_ADDR, 864
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setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
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#else
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setup_pll PLL1_BASE_ADDR, 800
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#endif
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setup_pll PLL3_BASE_ADDR, 665
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/* Switch peripheral to PLL 3 */
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
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str r1, [r0, #CLKCTL_CBCMR]
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ldr r1, =0x13239145
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str r1, [r0, #CLKCTL_CBCDR]
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setup_pll PLL2_BASE_ADDR, 665
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/* Switch peripheral to PLL2 */
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x19239145
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str r1, [r0, #CLKCTL_CBCDR]
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ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
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str r1, [r0, #CLKCTL_CBCMR]
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setup_pll PLL3_BASE_ADDR, 216
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/* Set the platform clock dividers */
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ldr r0, =ARM_BASE_ADDR
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ldr r1, =0x00000725
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str r1, [r0, #0x14]
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ldr r0, =CCM_BASE_ADDR
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/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
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ldr r3, [r4, #ROM_SI_REV]
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cmp r3, #0x10
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movls r1, #0x1
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movhi r1, #0
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str r1, [r0, #CLKCTL_CACRR]
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/* Switch ARM back to PLL 1 */
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str r4, [r0, #CLKCTL_CCSR]
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/* setup the rest */
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/* Use lp_apm (24MHz) source for perclk */
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ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
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str r1, [r0, #CLKCTL_CBCMR]
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/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
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ldr r1, =CONFIG_SYS_CLKTL_CBCDR
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str r1, [r0, #CLKCTL_CBCDR]
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/* Restore the default values in the Gate registers */
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ldr r1, =0xFFFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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str r1, [r0, #CLKCTL_CCGR1]
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str r1, [r0, #CLKCTL_CCGR2]
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str r1, [r0, #CLKCTL_CCGR3]
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str r1, [r0, #CLKCTL_CCGR4]
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str r1, [r0, #CLKCTL_CCGR5]
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str r1, [r0, #CLKCTL_CCGR6]
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/* Use PLL 2 for UART's, get 66.5MHz from it */
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ldr r1, =0xA5A2A020
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str r1, [r0, #CLKCTL_CSCMR1]
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ldr r1, =0x00C30321
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str r1, [r0, #CLKCTL_CSCDR1]
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/* make sure divider effective */
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1: ldr r1, [r0, #CLKCTL_CDHIPR]
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cmp r1, #0x0
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bne 1b
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str r4, [r0, #CLKCTL_CCDR]
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/* for cko - for ARM div by 8 */
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mov r1, #0x000A0000
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add r1, r1, #0x00000F0
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str r1, [r0, #CLKCTL_CCOSR]
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#else /* CONFIG_MX53 */
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ldr r0, =CCM_BASE_ADDR
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/* Gate of clocks to the peripherals first */
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ldr r1, =0x3FFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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str r4, [r0, #CLKCTL_CCGR1]
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str r4, [r0, #CLKCTL_CCGR2]
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str r4, [r0, #CLKCTL_CCGR3]
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str r4, [r0, #CLKCTL_CCGR7]
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ldr r1, =0x00030000
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str r1, [r0, #CLKCTL_CCGR4]
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ldr r1, =0x00FFF030
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str r1, [r0, #CLKCTL_CCGR5]
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ldr r1, =0x0F00030F
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str r1, [r0, #CLKCTL_CCGR6]
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/* Switch ARM to step clock */
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mov r1, #0x4
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str r1, [r0, #CLKCTL_CCSR]
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setup_pll PLL1_BASE_ADDR, 800
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setup_pll PLL3_BASE_ADDR, 400
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/* Switch peripheral to PLL3 */
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x00015154
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str r1, [r0, #CLKCTL_CBCMR]
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ldr r1, =0x02898945
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str r1, [r0, #CLKCTL_CBCDR]
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/* make sure change is effective */
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1: ldr r1, [r0, #CLKCTL_CDHIPR]
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cmp r1, #0x0
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bne 1b
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setup_pll PLL2_BASE_ADDR, 400
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/* Switch peripheral to PLL2 */
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x00888945
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str r1, [r0, #CLKCTL_CBCDR]
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ldr r1, =0x00016154
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str r1, [r0, #CLKCTL_CBCMR]
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/*change uart clk parent to pll2*/
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ldr r1, [r0, #CLKCTL_CSCMR1]
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and r1, r1, #0xfcffffff
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orr r1, r1, #0x01000000
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str r1, [r0, #CLKCTL_CSCMR1]
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/* make sure change is effective */
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1: ldr r1, [r0, #CLKCTL_CDHIPR]
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cmp r1, #0x0
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bne 1b
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setup_pll PLL3_BASE_ADDR, 216
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setup_pll PLL4_BASE_ADDR, 455
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/* Set the platform clock dividers */
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ldr r0, =ARM_BASE_ADDR
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ldr r1, =0x00000124
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str r1, [r0, #0x14]
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ldr r0, =CCM_BASE_ADDR
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mov r1, #0
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str r1, [r0, #CLKCTL_CACRR]
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/* Switch ARM back to PLL 1. */
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mov r1, #0x0
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str r1, [r0, #CLKCTL_CCSR]
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/* make uart div=6 */
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ldr r1, [r0, #CLKCTL_CSCDR1]
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and r1, r1, #0xffffffc0
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orr r1, r1, #0x0a
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str r1, [r0, #CLKCTL_CSCDR1]
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/* Restore the default values in the Gate registers */
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ldr r1, =0xFFFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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str r1, [r0, #CLKCTL_CCGR1]
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str r1, [r0, #CLKCTL_CCGR2]
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str r1, [r0, #CLKCTL_CCGR3]
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str r1, [r0, #CLKCTL_CCGR4]
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str r1, [r0, #CLKCTL_CCGR5]
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str r1, [r0, #CLKCTL_CCGR6]
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str r1, [r0, #CLKCTL_CCGR7]
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mov r1, #0x00000
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str r1, [r0, #CLKCTL_CCDR]
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/* for cko - for ARM div by 8 */
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mov r1, #0x000A0000
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add r1, r1, #0x00000F0
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str r1, [r0, #CLKCTL_CCOSR]
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#endif /* CONFIG_MX53 */
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.endm
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ENTRY(lowlevel_init)
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mov r10, lr
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mov r4, #0 /* Fix R4 to 0 */
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#if defined(CONFIG_SYS_MAIN_PWR_ON)
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ldr r0, =GPIO1_BASE_ADDR
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ldr r1, [r0, #0x0]
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orr r1, r1, #1 << 23
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str r1, [r0, #0x0]
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ldr r1, [r0, #0x4]
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orr r1, r1, #1 << 23
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str r1, [r0, #0x4]
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#endif
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init_arm_erratum
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init_l2cc
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init_aips
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init_m4if
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init_clock
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mov pc, r10
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ENDPROC(lowlevel_init)
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/* Board level setting value */
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#if defined(CONFIG_MX51_PLL_ERRATA)
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W_DP_864: .word DP_OP_864
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.word DP_MFD_864
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.word DP_MFN_864
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W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
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#else
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W_DP_800: .word DP_OP_800
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.word DP_MFD_800
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.word DP_MFN_800
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#endif
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#if defined(CONFIG_MX51)
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W_DP_665: .word DP_OP_665
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.word DP_MFD_665
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.word DP_MFN_665
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#endif
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W_DP_216: .word DP_OP_216
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.word DP_MFD_216
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.word DP_MFN_216
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W_DP_400: .word DP_OP_400
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.word DP_MFD_400
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.word DP_MFN_400
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W_DP_455: .word DP_OP_455
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.word DP_MFD_455
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.word DP_MFN_455
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