mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
35051db978
This adds USB nodes for MT7623/BPI-R2 Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
467 lines
12 KiB
Plaintext
467 lines
12 KiB
Plaintext
/*
|
|
* Copyright (C) 2018 MediaTek Inc.
|
|
* Author: Ryder Lee <ryder.lee@mediatek.com>
|
|
*
|
|
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
*/
|
|
|
|
#include <dt-bindings/clock/mt7623-clk.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/phy/phy.h>
|
|
#include <dt-bindings/power/mt7623-power.h>
|
|
#include <dt-bindings/reset/mt7623-reset.h>
|
|
#include "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "mediatek,mt7623";
|
|
interrupt-parent = <&sysirq>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
enable-method = "mediatek,mt6589-smp";
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x0>;
|
|
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
|
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
|
clock-names = "cpu", "intermediate";
|
|
clock-frequency = <1300000000>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x1>;
|
|
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
|
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
|
clock-names = "cpu", "intermediate";
|
|
clock-frequency = <1300000000>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x2>;
|
|
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
|
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
|
clock-names = "cpu", "intermediate";
|
|
clock-frequency = <1300000000>;
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x3>;
|
|
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
|
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
|
clock-names = "cpu", "intermediate";
|
|
clock-frequency = <1300000000>;
|
|
};
|
|
};
|
|
|
|
system_clk: dummy13m {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <13000000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
rtc32k: oscillator-1 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "rtc32k";
|
|
};
|
|
|
|
clk26m: oscillator-0 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <26000000>;
|
|
clock-output-names = "clk26m";
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
clock-frequency = <13000000>;
|
|
arm,cpu-registers-not-fw-configured;
|
|
};
|
|
|
|
topckgen: clock-controller@10000000 {
|
|
compatible = "mediatek,mt7623-topckgen";
|
|
reg = <0x10000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
infracfg: syscon@10001000 {
|
|
compatible = "mediatek,mt7623-infracfg", "syscon";
|
|
reg = <0x10001000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pericfg: syscon@10003000 {
|
|
compatible = "mediatek,mt7623-pericfg", "syscon";
|
|
reg = <0x10003000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pinctrl: pinctrl@10005000 {
|
|
compatible = "mediatek,mt7623-pinctrl";
|
|
reg = <0x10005000 0x1000>;
|
|
|
|
gpio: gpio-controller {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
};
|
|
|
|
scpsys: scpsys@10006000 {
|
|
compatible = "mediatek,mt7623-scpsys";
|
|
#power-domain-cells = <1>;
|
|
reg = <0x10006000 0x1000>;
|
|
infracfg = <&infracfg>;
|
|
clocks = <&topckgen CLK_TOP_MM_SEL>,
|
|
<&topckgen CLK_TOP_MFG_SEL>,
|
|
<&topckgen CLK_TOP_ETHIF_SEL>;
|
|
clock-names = "mm", "mfg", "ethif";
|
|
};
|
|
|
|
watchdog: watchdog@10007000 {
|
|
compatible = "mediatek,wdt";
|
|
reg = <0x10007000 0x100>;
|
|
};
|
|
|
|
wdt-reboot {
|
|
compatible = "wdt-reboot";
|
|
wdt = <&watchdog>;
|
|
};
|
|
|
|
timer0: timer@10008000 {
|
|
compatible = "mediatek,timer";
|
|
reg = <0x10008000 0x80>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&system_clk>;
|
|
clock-names = "system-clk";
|
|
};
|
|
|
|
sysirq: interrupt-controller@10200100 {
|
|
compatible = "mediatek,sysirq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&gic>;
|
|
reg = <0x10200100 0x1c>;
|
|
};
|
|
|
|
apmixedsys: clock-controller@10209000 {
|
|
compatible = "mediatek,mt7623-apmixedsys";
|
|
reg = <0x10209000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gic: interrupt-controller@10211000 {
|
|
compatible = "arm,cortex-a7-gic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&gic>;
|
|
reg = <0x10211000 0x1000>,
|
|
<0x10212000 0x1000>,
|
|
<0x10214000 0x2000>,
|
|
<0x10216000 0x2000>;
|
|
};
|
|
|
|
uart0: serial@11002000 {
|
|
compatible = "mediatek,hsuart";
|
|
reg = <0x11002000 0x400>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_UART_SEL>,
|
|
<&pericfg CLK_PERI_UART0>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@11003000 {
|
|
compatible = "mediatek,hsuart";
|
|
reg = <0x11003000 0x400>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_UART_SEL>,
|
|
<&pericfg CLK_PERI_UART1>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@11004000 {
|
|
compatible = "mediatek,hsuart";
|
|
reg = <0x11004000 0x400>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_UART_SEL>,
|
|
<&pericfg CLK_PERI_UART2>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@11005000 {
|
|
compatible = "mediatek,hsuart";
|
|
reg = <0x11005000 0x400>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_UART_SEL>,
|
|
<&pericfg CLK_PERI_UART3>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt7623-mmc";
|
|
reg = <0x11230000 0x1000>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_0>,
|
|
<&topckgen CLK_TOP_MSDC30_0_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@11240000 {
|
|
compatible = "mediatek,mt7623-mmc";
|
|
reg = <0x11240000 0x1000>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_1>,
|
|
<&topckgen CLK_TOP_MSDC30_1_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
hifsys: syscon@1a000000 {
|
|
compatible = "mediatek,mt7623-hifsys", "syscon";
|
|
reg = <0x1a000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
pcie: pcie@1a140000 {
|
|
compatible = "mediatek,mt7623-pcie";
|
|
device_type = "pci";
|
|
reg = <0x1a140000 0x1000>, /* PCIe shared registers */
|
|
<0x1a142000 0x1000>, /* Port0 registers */
|
|
<0x1a143000 0x1000>, /* Port1 registers */
|
|
<0x1a144000 0x1000>; /* Port2 registers */
|
|
reg-names = "subsys", "port0", "port1", "port2";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0xf800 0 0 0>;
|
|
interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
|
|
<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
|
|
<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
|
<&hifsys CLK_HIFSYS_PCIE0>,
|
|
<&hifsys CLK_HIFSYS_PCIE1>,
|
|
<&hifsys CLK_HIFSYS_PCIE2>;
|
|
clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
|
|
resets = <&hifsys HIFSYS_PCIE0_RST>,
|
|
<&hifsys HIFSYS_PCIE1_RST>,
|
|
<&hifsys HIFSYS_PCIE2_RST>;
|
|
reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
|
|
phys = <&pcie0_port PHY_TYPE_PCIE>,
|
|
<&pcie1_port PHY_TYPE_PCIE>,
|
|
<&u3port1 PHY_TYPE_PCIE>;
|
|
phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
|
|
power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
|
|
bus-range = <0x00 0xff>;
|
|
status = "disabled";
|
|
ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000
|
|
0x83000000 0 0x60000000 0x60000000 0 0x10000000>;
|
|
|
|
pcie@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
|
|
ranges;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie@1,0 {
|
|
reg = <0x0800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
|
|
ranges;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie@2,0 {
|
|
reg = <0x1000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
|
|
ranges;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pcie0_phy: pcie-phy@1a149000 {
|
|
compatible = "mediatek,generic-tphy-v1";
|
|
reg = <0x1a149000 0x0700>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
pcie0_port: pcie-phy@1a149900 {
|
|
reg = <0x1a149900 0x0700>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
pcie1_phy: pcie-phy@1a14a000 {
|
|
compatible = "mediatek,generic-tphy-v1";
|
|
reg = <0x1a14a000 0x0700>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
pcie1_port: pcie-phy@1a14a900 {
|
|
reg = <0x1a14a900 0x0700>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
usb1: usb@1a1c0000 {
|
|
compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
|
|
reg = <0x1a1c0000 0x1000>, <0x1a1c4700 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
|
|
clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
|
|
clock-names = "sys_ck", "ref_ck";
|
|
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
u3phy1: usb-phy@1a1c4000 {
|
|
compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1";
|
|
|
|
reg = <0x1a1c4000 0x0700>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
u2port0: usb-phy@1a1c4800 {
|
|
reg = <0x1a1c4800 0x0100>;
|
|
#phy-cells = <1>;
|
|
clocks = <&topckgen CLK_TOP_USB_PHY48M>;
|
|
clock-names = "ref";
|
|
};
|
|
|
|
u3port0: usb-phy@1a1c4900 {
|
|
reg = <0x1a1c4900 0x0700>;
|
|
#phy-cells = <1>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
};
|
|
};
|
|
|
|
usb2: usb@1a240000 {
|
|
compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
|
|
reg = <0x1a240000 0x1000>, <0x1a244700 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
|
|
clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
|
|
clock-names = "sys_ck", "ref_ck";
|
|
phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
u3phy2: usb-phy@1a244000 {
|
|
compatible = "mediatek,generic-tphy-v1";
|
|
reg = <0x1a244000 0x0700>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
u2port1: usb-phy@1a244800 {
|
|
reg = <0x1a244800 0x0100>;
|
|
clocks = <&topckgen CLK_TOP_USB_PHY48M>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
u3port1: usb-phy@1a244900 {
|
|
reg = <0x1a244900 0x0700>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
ethsys: syscon@1b000000 {
|
|
compatible = "mediatek,mt7623-ethsys", "syscon";
|
|
reg = <0x1b000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
eth: ethernet@1b100000 {
|
|
compatible = "mediatek,mt7623-eth", "syscon";
|
|
reg = <0x1b100000 0x20000>;
|
|
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
|
<ðsys CLK_ETHSYS_ESW>,
|
|
<ðsys CLK_ETHSYS_GP1>,
|
|
<ðsys CLK_ETHSYS_GP2>,
|
|
<&apmixedsys CLK_APMIXED_TRGPLL>;
|
|
clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
|
|
power-domains = <&scpsys MT7623_POWER_DOMAIN_ETH>;
|
|
resets = <ðsys ETHSYS_FE_RST>,
|
|
<ðsys ETHSYS_MCM_RST>;
|
|
reset-names = "fe", "mcm";
|
|
mediatek,ethsys = <ðsys>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@11006000 {
|
|
compatible = "mediatek,mt7623-pwm";
|
|
reg = <0x11006000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&topckgen CLK_TOP_PWM_SEL>,
|
|
<&pericfg CLK_PERI_PWM>,
|
|
<&pericfg CLK_PERI_PWM1>,
|
|
<&pericfg CLK_PERI_PWM2>,
|
|
<&pericfg CLK_PERI_PWM3>,
|
|
<&pericfg CLK_PERI_PWM4>,
|
|
<&pericfg CLK_PERI_PWM5>;
|
|
clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
|
|
"pwm5";
|
|
status = "disabled";
|
|
};
|
|
};
|