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a7fdac7e2a
Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
43 lines
906 B
Plaintext
43 lines
906 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LS1028A-QDS device tree fragment for RCW x5xx
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*
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* Copyright 2019-2021 NXP Semiconductors
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*/
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/*
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* This setup is using SCH-28021 cards with VSC8514 QSGMII PHY in slot 2.
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* This is only available on LS1028A QDS boards with lane B rework.
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*/
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&slot2 {
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#include "fsl-sch-28021.dtsi"
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};
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&mscc_felix {
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status = "okay";
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};
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&mscc_felix_port0 {
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status = "okay";
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phy-mode = "qsgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
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};
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&mscc_felix_port1 {
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status = "okay";
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phy-mode = "qsgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
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};
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&mscc_felix_port2 {
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status = "okay";
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phy-mode = "qsgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
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};
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&mscc_felix_port3 {
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status = "okay";
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phy-mode = "qsgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
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};
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