mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
83 lines
2.1 KiB
Plaintext
83 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Samsung Exynos7420 SoC device tree source
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*
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* Copyright (c) 2016 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/exynos7420-clk.h>
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/ {
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compatible = "samsung,exynos7420";
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fin_pll: xxti {
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compatible = "fixed-clock";
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clock-output-names = "fin_pll";
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u-boot,dm-pre-reloc;
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#clock-cells = <0>;
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};
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clock_topc: clock-controller@10570000 {
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compatible = "samsung,exynos7-clock-topc";
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reg = <0x10570000 0x10000>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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clocks = <&fin_pll>;
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clock-names = "fin_pll";
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};
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clock_top0: clock-controller@105d0000 {
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compatible = "samsung,exynos7-clock-top0";
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reg = <0x105d0000 0xb000>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
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<&clock_topc DOUT_SCLK_BUS1_PLL>,
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<&clock_topc DOUT_SCLK_CC_PLL>,
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<&clock_topc DOUT_SCLK_MFC_PLL>;
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clock-names = "fin_pll", "dout_sclk_bus0_pll",
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"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
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"dout_sclk_mfc_pll";
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};
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clock_peric1: clock-controller@14c80000 {
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compatible = "samsung,exynos7-clock-peric1";
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reg = <0x14c80000 0xd00>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
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<&clock_top0 CLK_SCLK_UART1>,
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<&clock_top0 CLK_SCLK_UART2>,
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<&clock_top0 CLK_SCLK_UART3>;
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clock-names = "fin_pll", "dout_aclk_peric1_66",
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"sclk_uart1", "sclk_uart2", "sclk_uart3";
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};
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pinctrl@13470000 {
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compatible = "samsung,exynos7420-pinctrl";
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reg = <0x13470000 0x1000>;
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u-boot,dm-pre-reloc;
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serial2_bus: serial2-bus {
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samsung,pins = "gpd1-4", "gpd1-5";
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samsung,pin-function = <2>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <0>;
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u-boot,dm-pre-reloc;
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};
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};
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serial@14C30000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14C30000 0x100>;
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u-boot,dm-pre-reloc;
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clocks = <&clock_peric1 PCLK_UART2>,
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<&clock_peric1 SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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pinctrl-names = "default";
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pinctrl-0 = <&serial2_bus>;
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};
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};
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