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https://github.com/brain-hackers/u-boot-brain
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Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
38 lines
1.2 KiB
Plaintext
38 lines
1.2 KiB
Plaintext
CORENET_DS BOARD
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#M: -
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S: Maintained
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F: board/freescale/corenet_ds/
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F: include/configs/P3041DS.h
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F: configs/P3041DS_defconfig
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F: configs/P3041DS_NAND_defconfig
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F: configs/P3041DS_SDCARD_defconfig
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F: configs/P3041DS_SECURE_BOOT_defconfig
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F: configs/P3041DS_SPIFLASH_defconfig
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F: configs/P3041DS_SRIO_PCIE_BOOT_defconfig
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F: include/configs/P4080DS.h
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F: configs/P4080DS_defconfig
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F: configs/P4080DS_SDCARD_defconfig
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F: configs/P4080DS_SECURE_BOOT_defconfig
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F: configs/P4080DS_SPIFLASH_defconfig
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F: configs/P4080DS_SRIO_PCIE_BOOT_defconfig
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F: include/configs/P5020DS.h
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F: configs/P5020DS_defconfig
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F: configs/P5020DS_NAND_defconfig
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F: configs/P5020DS_SDCARD_defconfig
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F: configs/P5020DS_SECURE_BOOT_defconfig
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F: configs/P5020DS_SPIFLASH_defconfig
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F: configs/P5020DS_SRIO_PCIE_BOOT_defconfig
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F: include/configs/P5040DS.h
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F: configs/P5040DS_defconfig
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F: configs/P5040DS_NAND_defconfig
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F: configs/P5040DS_SDCARD_defconfig
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F: configs/P5040DS_SPIFLASH_defconfig
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F: configs/P5040DS_SECURE_BOOT_defconfig
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CORENET_DS_SECURE_BOOT BOARD
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M: Aneesh Bansal <aneesh.bansal@freescale.com>
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S: Maintained
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F: configs/P3041DS_NAND_SECURE_BOOT_defconfig
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F: configs/P5020DS_NAND_SECURE_BOOT_defconfig
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F: configs/P5040DS_NAND_SECURE_BOOT_defconfig
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