mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-06 21:03:21 +09:00
![Masahiro Yamada](/assets/img/avatar_default.png)
This commit moves files as follows: arch/arm/cpu/arm720t/tegra20/* -> arch/arm/mach-tegra/tegra20/* arch/arm/cpu/arm720t/tegra30/* -> arch/arm/mach-tegra/tegra30/* arch/arm/cpu/arm720t/tegra114/* -> arch/arm/mach-tegra/tegra114/* arch/arm/cpu/arm720t/tegra124* -> arch/arm/mach-tegra/tegra124/* arch/arm/cpu/arm720t/tegra-common/* -> arch/arm/mach-tegra/* arch/arm/cpu/armv7/tegra20/* -> arch/arm/mach-tegra/tegra20/* arch/arm/cpu/armv7/tegra30/* -> arch/arm/mach-tegra/tegra30/* arch/arm/cpu/armv7/tegra114/* -> arch/arm/mach-tegra/tegra114/* arch/arm/cpu/armv7/tegra124/* -> arch/arm/mach-tegra/tegra124/* arch/arm/cpu/armv7/tegra-common/* -> arch/arm/mach-tegra/* arch/arm/cpu/tegra20-common/* -> arch/arm/mach-tegra/tegra20/* arch/arm/cpu/tegra30-common/* -> arch/arm/mach-tegra/tegra30/* arch/arm/cpu/tegra114-common/* -> arch/arm/mach-tegra/tegra114/* arch/arm/cpu/tegra124-common/* -> arch/arm/mach-tegra/tegra124/* arch/arm/cpu/tegra-common/* -> arch/arm/mach-tegra/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> [ on nyan-big ] Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
717 lines
17 KiB
C
717 lines
17 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/xusb-padctl.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
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#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
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enum tegra124_function {
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TEGRA124_FUNC_SNPS,
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TEGRA124_FUNC_XUSB,
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TEGRA124_FUNC_UART,
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TEGRA124_FUNC_PCIE,
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TEGRA124_FUNC_USB3,
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TEGRA124_FUNC_SATA,
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TEGRA124_FUNC_RSVD,
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};
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static const char *const tegra124_functions[] = {
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"snps",
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"xusb",
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"uart",
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"pcie",
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"usb3",
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"sata",
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"rsvd",
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};
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static const unsigned int tegra124_otg_functions[] = {
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TEGRA124_FUNC_SNPS,
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TEGRA124_FUNC_XUSB,
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TEGRA124_FUNC_UART,
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TEGRA124_FUNC_RSVD,
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};
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static const unsigned int tegra124_usb_functions[] = {
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TEGRA124_FUNC_SNPS,
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TEGRA124_FUNC_XUSB,
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};
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static const unsigned int tegra124_pci_functions[] = {
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TEGRA124_FUNC_PCIE,
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TEGRA124_FUNC_USB3,
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TEGRA124_FUNC_SATA,
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TEGRA124_FUNC_RSVD,
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};
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struct tegra_xusb_padctl_lane {
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const char *name;
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unsigned int offset;
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unsigned int shift;
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unsigned int mask;
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unsigned int iddq;
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const unsigned int *funcs;
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unsigned int num_funcs;
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};
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#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
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{ \
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.name = _name, \
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.offset = _offset, \
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.shift = _shift, \
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.mask = _mask, \
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.iddq = _iddq, \
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.num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
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.funcs = tegra124_##_funcs##_functions, \
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}
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static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
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TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
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TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
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TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
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TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
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TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
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TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
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TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
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TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
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TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
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TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
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TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
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TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
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};
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struct tegra_xusb_phy_ops {
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int (*prepare)(struct tegra_xusb_phy *phy);
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int (*enable)(struct tegra_xusb_phy *phy);
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int (*disable)(struct tegra_xusb_phy *phy);
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int (*unprepare)(struct tegra_xusb_phy *phy);
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};
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struct tegra_xusb_phy {
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const struct tegra_xusb_phy_ops *ops;
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struct tegra_xusb_padctl *padctl;
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};
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struct tegra_xusb_padctl_pin {
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const struct tegra_xusb_padctl_lane *lane;
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unsigned int func;
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int iddq;
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};
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#define MAX_GROUPS 3
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#define MAX_PINS 6
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struct tegra_xusb_padctl_group {
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const char *name;
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const char *pins[MAX_PINS];
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unsigned int num_pins;
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const char *func;
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int iddq;
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};
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struct tegra_xusb_padctl_config {
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const char *name;
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struct tegra_xusb_padctl_group groups[MAX_GROUPS];
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unsigned int num_groups;
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};
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struct tegra_xusb_padctl {
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struct fdt_resource regs;
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unsigned int enable;
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struct tegra_xusb_phy phys[2];
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const struct tegra_xusb_padctl_lane *lanes;
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unsigned int num_lanes;
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const char *const *functions;
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unsigned int num_functions;
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struct tegra_xusb_padctl_config config;
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};
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static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
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unsigned long offset)
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{
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return readl(padctl->regs.start + offset);
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}
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static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
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u32 value, unsigned long offset)
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{
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writel(value, padctl->regs.start + offset);
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}
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static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
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{
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u32 value;
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if (padctl->enable++ > 0)
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return 0;
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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return 0;
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}
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static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
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{
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u32 value;
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if (padctl->enable == 0) {
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error("tegra-xusb-padctl: unbalanced enable/disable");
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return 0;
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}
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if (--padctl->enable > 0)
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return 0;
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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return 0;
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}
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static int phy_prepare(struct tegra_xusb_phy *phy)
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{
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return tegra_xusb_padctl_enable(phy->padctl);
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}
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static int phy_unprepare(struct tegra_xusb_phy *phy)
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{
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return tegra_xusb_padctl_disable(phy->padctl);
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}
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static int pcie_phy_enable(struct tegra_xusb_phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy->padctl;
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int err = -ETIMEDOUT;
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unsigned long start;
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
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value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
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XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
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XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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start = get_timer(0);
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while (get_timer(start) < 50) {
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
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err = 0;
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break;
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}
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}
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return err;
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}
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static int pcie_phy_disable(struct tegra_xusb_phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy->padctl;
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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return 0;
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}
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static int sata_phy_enable(struct tegra_xusb_phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy->padctl;
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int err = -ETIMEDOUT;
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unsigned long start;
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
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value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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start = get_timer(0);
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while (get_timer(start) < 50) {
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
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err = 0;
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break;
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}
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}
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return err;
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}
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static int sata_phy_disable(struct tegra_xusb_phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy->padctl;
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
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value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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return 0;
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}
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static const struct tegra_xusb_phy_ops pcie_phy_ops = {
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.prepare = phy_prepare,
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.enable = pcie_phy_enable,
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.disable = pcie_phy_disable,
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.unprepare = phy_unprepare,
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};
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static const struct tegra_xusb_phy_ops sata_phy_ops = {
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.prepare = phy_prepare,
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.enable = sata_phy_enable,
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.disable = sata_phy_disable,
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.unprepare = phy_unprepare,
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};
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static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
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.phys = {
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[0] = {
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.ops = &pcie_phy_ops,
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},
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[1] = {
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.ops = &sata_phy_ops,
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},
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},
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};
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static const struct tegra_xusb_padctl_lane *
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tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
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{
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unsigned int i;
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for (i = 0; i < padctl->num_lanes; i++)
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if (strcmp(name, padctl->lanes[i].name) == 0)
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return &padctl->lanes[i];
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return NULL;
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}
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static int
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tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
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struct tegra_xusb_padctl_group *group,
|
|
const void *fdt, int node)
|
|
{
|
|
unsigned int i;
|
|
int len, err;
|
|
|
|
group->name = fdt_get_name(fdt, node, &len);
|
|
|
|
len = fdt_count_strings(fdt, node, "nvidia,lanes");
|
|
if (len < 0) {
|
|
error("tegra-xusb-padctl: failed to parse \"nvidia,lanes\" property");
|
|
return -EINVAL;
|
|
}
|
|
|
|
group->num_pins = len;
|
|
|
|
for (i = 0; i < group->num_pins; i++) {
|
|
err = fdt_get_string_index(fdt, node, "nvidia,lanes", i,
|
|
&group->pins[i]);
|
|
if (err < 0) {
|
|
error("tegra-xusb-padctl: failed to read string from \"nvidia,lanes\" property");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
group->num_pins = len;
|
|
|
|
err = fdt_get_string(fdt, node, "nvidia,function", &group->func);
|
|
if (err < 0) {
|
|
error("tegra-xusb-padctl: failed to parse \"nvidia,func\" property");
|
|
return -EINVAL;
|
|
}
|
|
|
|
group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
|
|
const char *name)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < padctl->num_functions; i++)
|
|
if (strcmp(name, padctl->functions[i]) == 0)
|
|
return i;
|
|
|
|
return -ENOENT;
|
|
}
|
|
|
|
static int
|
|
tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
|
|
const struct tegra_xusb_padctl_lane *lane,
|
|
const char *name)
|
|
{
|
|
unsigned int i;
|
|
int func;
|
|
|
|
func = tegra_xusb_padctl_find_function(padctl, name);
|
|
if (func < 0)
|
|
return func;
|
|
|
|
for (i = 0; i < lane->num_funcs; i++)
|
|
if (lane->funcs[i] == func)
|
|
return i;
|
|
|
|
return -ENOENT;
|
|
}
|
|
|
|
static int
|
|
tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
|
|
const struct tegra_xusb_padctl_group *group)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < group->num_pins; i++) {
|
|
const struct tegra_xusb_padctl_lane *lane;
|
|
unsigned int func;
|
|
u32 value;
|
|
|
|
lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
|
|
if (!lane) {
|
|
error("tegra-xusb-padctl: no lane for pin %s",
|
|
group->pins[i]);
|
|
continue;
|
|
}
|
|
|
|
func = tegra_xusb_padctl_lane_find_function(padctl, lane,
|
|
group->func);
|
|
if (func < 0) {
|
|
error("tegra-xusb-padctl: function %s invalid for lane %s: %d",
|
|
group->func, lane->name, func);
|
|
continue;
|
|
}
|
|
|
|
value = padctl_readl(padctl, lane->offset);
|
|
|
|
/* set pin function */
|
|
value &= ~(lane->mask << lane->shift);
|
|
value |= func << lane->shift;
|
|
|
|
/*
|
|
* Set IDDQ if supported on the lane and specified in the
|
|
* configuration.
|
|
*/
|
|
if (lane->iddq > 0 && group->iddq >= 0) {
|
|
if (group->iddq != 0)
|
|
value &= ~(1 << lane->iddq);
|
|
else
|
|
value |= 1 << lane->iddq;
|
|
}
|
|
|
|
padctl_writel(padctl, value, lane->offset);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
|
|
struct tegra_xusb_padctl_config *config)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < config->num_groups; i++) {
|
|
const struct tegra_xusb_padctl_group *group;
|
|
int err;
|
|
|
|
group = &config->groups[i];
|
|
|
|
err = tegra_xusb_padctl_group_apply(padctl, group);
|
|
if (err < 0) {
|
|
error("tegra-xusb-padctl: failed to apply group %s: %d",
|
|
group->name, err);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
|
|
struct tegra_xusb_padctl_config *config,
|
|
const void *fdt, int node)
|
|
{
|
|
int subnode;
|
|
|
|
config->name = fdt_get_name(fdt, node, NULL);
|
|
|
|
fdt_for_each_subnode(fdt, subnode, node) {
|
|
struct tegra_xusb_padctl_group *group;
|
|
int err;
|
|
|
|
group = &config->groups[config->num_groups];
|
|
|
|
err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
|
|
subnode);
|
|
if (err < 0) {
|
|
error("tegra-xusb-padctl: failed to parse group %s",
|
|
group->name);
|
|
return err;
|
|
}
|
|
|
|
config->num_groups++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
|
|
const void *fdt, int node)
|
|
{
|
|
int subnode, err;
|
|
|
|
err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
|
|
if (err < 0) {
|
|
error("tegra-xusb-padctl: registers not found");
|
|
return err;
|
|
}
|
|
|
|
fdt_for_each_subnode(fdt, subnode, node) {
|
|
struct tegra_xusb_padctl_config *config = &padctl->config;
|
|
|
|
err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
|
|
subnode);
|
|
if (err < 0) {
|
|
error("tegra-xusb-padctl: failed to parse entry %s: %d",
|
|
config->name, err);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int process_nodes(const void *fdt, int nodes[], unsigned int count)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
enum fdt_compat_id id;
|
|
int err;
|
|
|
|
if (!fdtdec_get_is_enabled(fdt, nodes[i]))
|
|
continue;
|
|
|
|
id = fdtdec_lookup(fdt, nodes[i]);
|
|
switch (id) {
|
|
case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
|
|
break;
|
|
|
|
default:
|
|
error("tegra-xusb-padctl: unsupported compatible: %s",
|
|
fdtdec_get_compatible(id));
|
|
continue;
|
|
}
|
|
|
|
padctl->num_lanes = ARRAY_SIZE(tegra124_lanes);
|
|
padctl->lanes = tegra124_lanes;
|
|
|
|
padctl->num_functions = ARRAY_SIZE(tegra124_functions);
|
|
padctl->functions = tegra124_functions;
|
|
|
|
err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
|
|
if (err < 0) {
|
|
error("tegra-xusb-padctl: failed to parse DT: %d",
|
|
err);
|
|
continue;
|
|
}
|
|
|
|
/* deassert XUSB padctl reset */
|
|
reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
|
|
|
|
err = tegra_xusb_padctl_config_apply(padctl, &padctl->config);
|
|
if (err < 0) {
|
|
error("tegra-xusb-padctl: failed to apply pinmux: %d",
|
|
err);
|
|
continue;
|
|
}
|
|
|
|
/* only a single instance is supported */
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
|
|
{
|
|
struct tegra_xusb_phy *phy = NULL;
|
|
|
|
switch (type) {
|
|
case TEGRA_XUSB_PADCTL_PCIE:
|
|
phy = &padctl->phys[0];
|
|
phy->padctl = padctl;
|
|
break;
|
|
|
|
case TEGRA_XUSB_PADCTL_SATA:
|
|
phy = &padctl->phys[1];
|
|
phy->padctl = padctl;
|
|
break;
|
|
}
|
|
|
|
return phy;
|
|
}
|
|
|
|
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
|
|
{
|
|
if (phy && phy->ops && phy->ops->prepare)
|
|
return phy->ops->prepare(phy);
|
|
|
|
return phy ? -ENOSYS : -EINVAL;
|
|
}
|
|
|
|
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
|
|
{
|
|
if (phy && phy->ops && phy->ops->enable)
|
|
return phy->ops->enable(phy);
|
|
|
|
return phy ? -ENOSYS : -EINVAL;
|
|
}
|
|
|
|
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
|
|
{
|
|
if (phy && phy->ops && phy->ops->disable)
|
|
return phy->ops->disable(phy);
|
|
|
|
return phy ? -ENOSYS : -EINVAL;
|
|
}
|
|
|
|
int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
|
|
{
|
|
if (phy && phy->ops && phy->ops->unprepare)
|
|
return phy->ops->unprepare(phy);
|
|
|
|
return phy ? -ENOSYS : -EINVAL;
|
|
}
|
|
|
|
void tegra_xusb_padctl_init(const void *fdt)
|
|
{
|
|
int count, nodes[1];
|
|
|
|
count = fdtdec_find_aliases_for_id(fdt, "padctl",
|
|
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
|
|
nodes, ARRAY_SIZE(nodes));
|
|
if (process_nodes(fdt, nodes, count))
|
|
return;
|
|
}
|