York Sun 73b5396b25 powerpc/mpc8xxx: Add fine timing support for DDR3 ... When the DDR3 speed goes higher, we need to utilize fine offset from SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>		2012-08-23 12:16:55 -05:00
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ddr	powerpc/mpc8xxx: Add fine timing support for DDR3	2012-08-23 12:16:55 -05:00
cpu.c	powerpc/mpc8xxx: use topology registers to calculate number of cores	2012-08-23 12:16:54 -05:00
fdt.c	powerpc/mpc8xxx: fix core id for multicore booting	2012-08-23 12:16:55 -05:00
fsl_ifc.c	Added new ext fields to IFC	2012-08-23 12:16:55 -05:00
fsl_lbc.c	fsl_lbc: add printout of LCRR and LBCR to local bus regs	2012-01-13 12:56:06 -06:00
Makefile	powerpc/85xx: Add support for Integrated Flash Controller (IFC)	2011-04-04 09:24:40 -05:00
srio.c	powerpc/corenet_ds: Master module for boot from PCIE	2012-08-23 10:24:15 -05:00