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![Stefan Roese](/assets/img/avatar_default.png)
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*-----------------------------------------------------------------------
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* Timer value for timer 2, ICLK = 10
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*
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* SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
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* SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
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*
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* SPEED_FCOUNT2 timer 2 counting frequency
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* GCLK CPU clock
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* SPEED_TMR2_PS prescaler
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*/
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#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
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/*-----------------------------------------------------------------------
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* Timer value for PIT
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*
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* PIT_TIME = SPEED_PITC / PITRTCLK
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* PITRTCLK = 8192
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*/
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#define SPEED_PITC (82 << 16) /* start counting from 82 */
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/*
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* The new value for PTA is calculated from
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*
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* PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
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*
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* gclk CPU clock (not bus clock !)
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* Trefresh Refresh cycle * 4 (four word bursts used)
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* DFBRG For normal mode (no clock reduction) always 0
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* PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
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* NCS Number of SDRAM banks (chip selects) on this UPM.
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*/
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