mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
96 lines
3.0 KiB
C
96 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015 General Electric Company
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*/
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#ifndef __PPD_GPIO_H_
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#define __PPD_GPIO_H_
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#include <asm/arch/iomux-mx53.h>
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#include <asm/gpio.h>
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#define PPD_UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP)
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static const iomux_v3_cfg_t ppd_pads[] = {
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/* FEC */
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MX53_PAD_EIM_A22__GPIO2_16,
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/* UART */
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NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, PPD_UART_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, PPD_UART_PAD_CTRL),
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/* Video */
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MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */
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MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */
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MX53_PAD_CSI0_DAT10__GPIO5_28, /* DATA_WIDTH_CTRL */
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MX53_PAD_CSI0_PIXCLK__GPIO5_18, /* HOST_CONTROLLED_RESET_TO_LCD_N */
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MX53_PAD_EIM_DA2__GPIO3_2, /* LVDS1_MUX_CTRL */
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MX53_PAD_EIM_DA3__GPIO3_3, /* LVDS0_MUX_CTRL */
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MX53_PAD_EIM_A21__GPIO2_17, /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */
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MX53_PAD_CSI0_DAT11__GPIO5_29, /* BACKLIGHT_ENABLE */
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MX53_PAD_DISP0_DAT9__PWM2_PWMO, /* IMX535_PWM2_TO_LCD_CONNECTOR */
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/* I2C */
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MX53_PAD_EIM_A20__GPIO2_18, /* RESET_I2C1_BUS_SEGMENT_MUX_N */
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/* SPI */
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MX53_PAD_DISP0_DAT23__GPIO5_17,
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MX53_PAD_KEY_COL2__GPIO4_10,
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MX53_PAD_KEY_ROW2__GPIO4_11,
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MX53_PAD_KEY_COL3__GPIO4_12,
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};
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struct gpio_cfg {
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unsigned int gpio;
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int value;
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};
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#define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16)
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#define UD_SCAN_CTRL IMX_GPIO_NR(5, 21)
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#define LR_SCAN_CTRL IMX_GPIO_NR(5, 20)
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#define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3)
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#define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2)
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#define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18)
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#define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28)
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#define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28)
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#define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29)
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#define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22)
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#define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27)
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#define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17)
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#define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29)
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#define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18)
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#define ECSPI1_CS0 IMX_GPIO_NR(5, 17)
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#define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
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#define ECSPI1_CS2 IMX_GPIO_NR(4, 11)
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#define ECSPI1_CS3 IMX_GPIO_NR(4, 12)
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static const struct gpio_cfg ppd_gpios[] = {
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/* FEC */
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/* Drive Low as GPIO output for 25ms per Eth Phy IX spec */
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/* Then Drive High as GPIO output to bring Eth Phy IC out of reset */
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{ RESET_IMX535_ETHERNET_PHY_N, 0 },
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{ RESET_IMX535_ETHERNET_PHY_N, 1 },
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/* Video */
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{ UD_SCAN_CTRL, 0 },
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{ LR_SCAN_CTRL, 1 },
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#ifdef PROPRIETARY_CHANGES
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{ LVDS0_MUX_CTRL, 1 },
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#else
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{ LVDS0_MUX_CTRL, 0 },
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#endif
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{ LVDS1_MUX_CTRL, 1 },
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{ HOST_CONTROLLED_RESET_TO_LCD_N, 1 },
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{ DATA_WIDTH_CTRL, 0 },
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{ RESET_DP0_TRANSMITTER_N, 1 },
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{ RESET_DP1_TRANSMITTER_N, 1 },
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{ POWER_DOWN_LVDS0_DESERIALIZER_N, 1 },
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{ POWER_DOWN_LVDS1_DESERIALIZER_N, 1 },
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{ ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 },
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{ BACKLIGHT_ENABLE, 0 },
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{ RESET_I2C1_BUS_SEGMENT_MUX_N, 1 },
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{ ECSPI1_CS0, 1 },
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{ ECSPI1_CS1, 1 },
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{ ECSPI1_CS2, 1 },
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{ ECSPI1_CS3, 1 },
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};
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#endif /* __PPD_GPIO_H_ */
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