mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
731fd50e27
The AV96 board does exist in multiple variants. To cater for all of them, implement board code handling. There are two GPIOs which code the type of the board, read them out and use the value to pick the correct device tree from an fitImage. Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Change-Id: Iddb330b9a66500495885457cbe17edc0eacaaf43
319 lines
6.1 KiB
Plaintext
319 lines
6.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
/*
|
|
* Copyright (C) 2019 Marek Vasut <marex@denx.de>
|
|
*/
|
|
|
|
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
|
#include "stm32mp15-u-boot.dtsi"
|
|
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
|
|
|
/ {
|
|
aliases {
|
|
i2c1 = &i2c2;
|
|
i2c3 = &i2c4;
|
|
i2c4 = &i2c5;
|
|
mmc0 = &sdmmc1;
|
|
mmc1 = &sdmmc2;
|
|
spi0 = &qspi;
|
|
usb0 = &usbotg_hs;
|
|
};
|
|
|
|
config {
|
|
u-boot,boot-led = "heartbeat";
|
|
u-boot,error-led = "error";
|
|
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
|
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
|
|
dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
|
|
};
|
|
|
|
led {
|
|
red {
|
|
label = "error";
|
|
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
|
default-state = "off";
|
|
status = "okay";
|
|
};
|
|
|
|
blue {
|
|
default-state = "on";
|
|
};
|
|
};
|
|
|
|
/* This is actually on FMC2, but we do not have bus driver for that */
|
|
ksz8851: ks8851mll@64000000 {
|
|
compatible = "micrel,ks8851-mll";
|
|
reg = <0x64000000 0x20000>;
|
|
};
|
|
};
|
|
|
|
&i2c4 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&i2c4_pins_a {
|
|
u-boot,dm-pre-reloc;
|
|
pins {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
&pinctrl {
|
|
/* These should bound to FMC2 bus driver, but we do not have one */
|
|
pinctrl-0 = <&fmc_pins_b>;
|
|
pinctrl-1 = <&fmc_sleep_pins_b>;
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
fmc_pins_b: fmc-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
|
|
<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
|
|
<STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
|
|
<STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
|
|
<STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
|
|
<STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
|
|
<STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
|
|
<STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
|
|
<STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
|
|
<STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
|
|
<STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
|
|
<STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
|
|
<STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
|
|
<STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
|
|
<STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
|
|
<STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
|
|
<STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
|
|
<STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
|
|
<STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
|
|
<STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
|
|
<STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <3>;
|
|
};
|
|
};
|
|
|
|
fmc_sleep_pins_b: fmc-sleep-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
|
|
<STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
|
|
<STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
|
|
<STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
|
|
<STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
|
|
<STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
|
|
<STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
|
|
<STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
|
|
<STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
|
|
<STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
|
|
<STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
|
|
<STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
|
|
<STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
|
|
<STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
|
|
<STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
|
|
<STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
|
|
<STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
|
|
<STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
|
|
<STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
|
|
<STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
|
|
<STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
|
|
};
|
|
};
|
|
};
|
|
|
|
&pmic {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&flash0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&qspi {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&qspi_clk_pins_a {
|
|
u-boot,dm-spl;
|
|
pins {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&qspi_bk1_pins_a {
|
|
u-boot,dm-spl;
|
|
pins1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
pins2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&qspi_bk2_pins_a {
|
|
u-boot,dm-spl;
|
|
pins1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
pins2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&rcc {
|
|
st,clksrc = <
|
|
CLK_MPU_PLL1P
|
|
CLK_AXI_PLL2P
|
|
CLK_MCU_PLL3P
|
|
CLK_PLL12_HSE
|
|
CLK_PLL3_HSE
|
|
CLK_PLL4_HSE
|
|
CLK_RTC_LSE
|
|
CLK_MCO1_DISABLED
|
|
CLK_MCO2_DISABLED
|
|
>;
|
|
|
|
st,clkdiv = <
|
|
1 /*MPU*/
|
|
0 /*AXI*/
|
|
0 /*MCU*/
|
|
1 /*APB1*/
|
|
1 /*APB2*/
|
|
1 /*APB3*/
|
|
1 /*APB4*/
|
|
2 /*APB5*/
|
|
23 /*RTC*/
|
|
0 /*MCO1*/
|
|
0 /*MCO2*/
|
|
>;
|
|
|
|
st,pkcs = <
|
|
CLK_CKPER_HSE
|
|
CLK_FMC_ACLK
|
|
CLK_QSPI_ACLK
|
|
CLK_ETH_PLL4P
|
|
CLK_SDMMC12_PLL4P
|
|
CLK_DSI_DSIPLL
|
|
CLK_STGEN_HSE
|
|
CLK_USBPHY_HSE
|
|
CLK_SPI2S1_PLL3Q
|
|
CLK_SPI2S23_PLL3Q
|
|
CLK_SPI45_HSI
|
|
CLK_SPI6_HSI
|
|
CLK_I2C46_HSI
|
|
CLK_SDMMC3_PLL4P
|
|
CLK_USBO_USBPHY
|
|
CLK_ADC_CKPER
|
|
CLK_CEC_LSE
|
|
CLK_I2C12_HSI
|
|
CLK_I2C35_HSI
|
|
CLK_UART1_HSI
|
|
CLK_UART24_HSI
|
|
CLK_UART35_HSI
|
|
CLK_UART6_HSI
|
|
CLK_UART78_HSI
|
|
CLK_SPDIF_PLL4P
|
|
CLK_FDCAN_PLL4R
|
|
CLK_SAI1_PLL3Q
|
|
CLK_SAI2_PLL3Q
|
|
CLK_SAI3_PLL3Q
|
|
CLK_SAI4_PLL3Q
|
|
CLK_RNG1_LSI
|
|
CLK_RNG2_LSI
|
|
CLK_LPTIM1_PCLK1
|
|
CLK_LPTIM23_PCLK3
|
|
CLK_LPTIM45_LSE
|
|
>;
|
|
|
|
/* VCO = 1300.0 MHz => P = 650 (CPU) */
|
|
pll1: st,pll@0 {
|
|
compatible = "st,stm32mp1-pll";
|
|
reg = <0>;
|
|
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
|
|
frac = < 0x800 >;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
|
pll2: st,pll@1 {
|
|
compatible = "st,stm32mp1-pll";
|
|
reg = <1>;
|
|
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
|
frac = < 0x1400 >;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
|
pll3: st,pll@2 {
|
|
compatible = "st,stm32mp1-pll";
|
|
reg = <2>;
|
|
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
|
|
frac = < 0x1a04 >;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
/* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
|
|
pll4: st,pll@3 {
|
|
compatible = "st,stm32mp1-pll";
|
|
reg = <3>;
|
|
cfg = < 1 49 11 11 11 PQR(1,1,1) >;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
&sdmmc1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&sdmmc1_b4_pins_a {
|
|
u-boot,dm-spl;
|
|
pins1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
pins2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&sdmmc1_dir_pins_a {
|
|
u-boot,dm-spl;
|
|
pins1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
pins2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&sdmmc2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&sdmmc2_b4_pins_a {
|
|
u-boot,dm-spl;
|
|
pins {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&sdmmc2_d47_pins_a {
|
|
u-boot,dm-spl;
|
|
pins {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&uart4 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&uart4_pins_a {
|
|
u-boot,dm-pre-reloc;
|
|
pins1 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
pins2 {
|
|
u-boot,dm-pre-reloc;
|
|
/* pull-up on rx to avoid floating level */
|
|
bias-pull-up;
|
|
};
|
|
};
|