mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 03:19:43 +09:00
ffdf9f9ae0
This is based on Thierry Reding's work and uses Ian Campell's preparatory patches. It comes with full support for CPU_ON/OFF PSCI services. The algorithm used in this version for turning CPUs on and off was proposed by Peter De Schrijver and Thierry Reding in http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It consists of first enabling CPU1..3 via the PMC, just to powergate them again with the help of the Flow Controller. Once the Flow Controller is in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF PSCI requests. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
102 lines
2.0 KiB
ArmAsm
102 lines
2.0 KiB
ArmAsm
/*
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* Copyright (C) 2014, NVIDIA
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* Copyright (C) 2015, Siemens AG
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*
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* Authors:
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* Thierry Reding <treding@nvidia.com>
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/psci.h>
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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#define TEGRA_SB_CSR_0 0x6000c200
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#define NS_RST_VEC_WR_DIS (1 << 1)
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#define TEGRA_RESET_EXCEPTION_VECTOR 0x6000f100
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#define TEGRA_FLOW_CTRL_BASE 0x60007000
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#define FLOW_CTRL_CPU_CSR 0x08
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#define CSR_ENABLE (1 << 0)
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#define CSR_IMMEDIATE_WAKE (1 << 3)
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#define CSR_WAIT_WFI_SHIFT 8
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#define FLOW_CTRL_CPU1_CSR 0x18
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@ converts CPU ID into FLOW_CTRL_CPUn_CSR offset
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.macro get_csr_reg cpu, ofs, tmp
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cmp \cpu, #0 @ CPU0?
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lsl \tmp, \cpu, #3 @ multiple by 8 (register offset CPU1-3)
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moveq \ofs, #FLOW_CTRL_CPU_CSR
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addne \ofs, \tmp, #FLOW_CTRL_CPU1_CSR - 8
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.endm
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ENTRY(psci_arch_init)
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mov r6, lr
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mrc p15, 0, r5, c1, c1, 0 @ Read SCR
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bic r5, r5, #1 @ Secure mode
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mcr p15, 0, r5, c1, c1, 0 @ Write SCR
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isb
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@ lock reset vector for non-secure
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ldr r4, =TEGRA_SB_CSR_0
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ldr r5, [r4]
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orr r5, r5, #NS_RST_VEC_WR_DIS
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str r5, [r4]
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bl psci_get_cpu_id @ CPU ID => r0
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bl psci_get_cpu_stack_top @ stack top => r0
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mov sp, r0
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bx r6
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ENDPROC(psci_arch_init)
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ENTRY(psci_cpu_off)
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bl psci_cpu_off_common
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bl psci_get_cpu_id @ CPU ID => r0
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get_csr_reg r0, r2, r3
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ldr r6, =TEGRA_FLOW_CTRL_BASE
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mov r5, #(CSR_ENABLE)
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mov r4, #(1 << CSR_WAIT_WFI_SHIFT)
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add r5, r4, lsl r0
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str r5, [r6, r2]
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_loop: wfi
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b _loop
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ENDPROC(psci_cpu_off)
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ENTRY(psci_cpu_on)
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push {lr}
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mov r0, r1
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bl psci_get_cpu_stack_top @ get stack top of target CPU
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str r2, [r0] @ store target PC at stack top
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dsb
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ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
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ldr r5, =psci_cpu_entry
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str r5, [r6]
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get_csr_reg r1, r2, r3
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ldr r6, =TEGRA_FLOW_CTRL_BASE
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mov r5, #(CSR_IMMEDIATE_WAKE | CSR_ENABLE)
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str r5, [r6, r2]
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mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
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pop {pc}
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ENDPROC(psci_cpu_on)
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.globl psci_text_end
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psci_text_end:
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.popsection
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