mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
470 lines
15 KiB
C
470 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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* Based on Atheros LSDK/QSDK
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ath79.h>
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#define DDR_CTRL_UPD_EMR3S BIT(5)
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#define DDR_CTRL_UPD_EMR2S BIT(4)
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#define DDR_CTRL_PRECHARGE BIT(3)
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#define DDR_CTRL_AUTO_REFRESH BIT(2)
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#define DDR_CTRL_UPD_EMRS BIT(1)
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#define DDR_CTRL_UPD_MRS BIT(0)
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#define DDR_REFRESH_EN BIT(14)
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#define DDR_REFRESH_M 0x3ff
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#define DDR_REFRESH(x) ((x) & DDR_REFRESH_M)
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#define DDR_REFRESH_VAL (DDR_REFRESH_EN | DDR_REFRESH(312))
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#define DDR_TRAS_S 0
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#define DDR_TRAS_M 0x1f
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#define DDR_TRAS(x) (((x) & DDR_TRAS_M) << DDR_TRAS_S)
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#define DDR_TRCD_M 0xf
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#define DDR_TRCD_S 5
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#define DDR_TRCD(x) (((x) & DDR_TRCD_M) << DDR_TRCD_S)
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#define DDR_TRP_M 0xf
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#define DDR_TRP_S 9
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#define DDR_TRP(x) (((x) & DDR_TRP_M) << DDR_TRP_S)
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#define DDR_TRRD_M 0xf
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#define DDR_TRRD_S 13
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#define DDR_TRRD(x) (((x) & DDR_TRRD_M) << DDR_TRRD_S)
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#define DDR_TRFC_M 0x7f
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#define DDR_TRFC_S 17
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#define DDR_TRFC(x) (((x) & DDR_TRFC_M) << DDR_TRFC_S)
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#define DDR_TMRD_M 0xf
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#define DDR_TMRD_S 23
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#define DDR_TMRD(x) (((x) & DDR_TMRD_M) << DDR_TMRD_S)
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#define DDR_CAS_L_M 0x17
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#define DDR_CAS_L_S 27
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#define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
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#define DDR_OPEN BIT(30)
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#define DDR1_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \
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DDR_TRP(6) | DDR_TRRD(4) | \
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DDR_TRFC(7) | DDR_TMRD(5) | \
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DDR_CAS_L(7) | DDR_OPEN)
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#define DDR2_CONF_REG_VAL (DDR_TRAS(27) | DDR_TRCD(9) | \
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DDR_TRP(9) | DDR_TRRD(7) | \
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DDR_TRFC(21) | DDR_TMRD(15) | \
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DDR_CAS_L(17) | DDR_OPEN)
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#define DDR_BURST_LEN_S 0
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#define DDR_BURST_LEN_M 0xf
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#define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S)
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#define DDR_BURST_TYPE BIT(4)
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#define DDR_CNTL_OE_EN BIT(5)
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#define DDR_PHASE_SEL BIT(6)
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#define DDR_CKE BIT(7)
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#define DDR_TWR_S 8
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#define DDR_TWR_M 0xf
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#define DDR_TWR(x) (((x) & DDR_TWR_M) << DDR_TWR_S)
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#define DDR_TRTW_S 12
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#define DDR_TRTW_M 0x1f
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#define DDR_TRTW(x) (((x) & DDR_TRTW_M) << DDR_TRTW_S)
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#define DDR_TRTP_S 17
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#define DDR_TRTP_M 0xf
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#define DDR_TRTP(x) (((x) & DDR_TRTP_M) << DDR_TRTP_S)
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#define DDR_TWTR_S 21
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#define DDR_TWTR_M 0x1f
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#define DDR_TWTR(x) (((x) & DDR_TWTR_M) << DDR_TWTR_S)
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#define DDR_G_OPEN_L_S 26
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#define DDR_G_OPEN_L_M 0xf
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#define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S)
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#define DDR_HALF_WIDTH_LOW BIT(31)
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#define DDR1_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
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DDR_CKE | DDR_TWR(13) | DDR_TRTW(14) | \
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DDR_TRTP(8) | DDR_TWTR(14) | \
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DDR_G_OPEN_L(6) | DDR_HALF_WIDTH_LOW)
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#define DDR2_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
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DDR_CKE | DDR_TWR(1) | DDR_TRTW(14) | \
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DDR_TRTP(9) | DDR_TWTR(21) | \
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DDR_G_OPEN_L(8) | DDR_HALF_WIDTH_LOW)
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#define DDR_TWR_MSB BIT(3)
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#define DDR_TRAS_MSB BIT(2)
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#define DDR_TRFC_MSB_M 0x3
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#define DDR_TRFC_MSB(x) (x)
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#define DDR1_CONF3_REG_VAL 0
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#define DDR2_CONF3_REG_VAL (DDR_TWR_MSB | DDR_TRFC_MSB(2))
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#define DDR_CTL_SRAM_TSEL BIT(30)
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#define DDR_CTL_SRAM_GE0_SYNC BIT(20)
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#define DDR_CTL_SRAM_GE1_SYNC BIT(19)
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#define DDR_CTL_SRAM_USB_SYNC BIT(18)
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#define DDR_CTL_SRAM_PCIE_SYNC BIT(17)
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#define DDR_CTL_SRAM_WMAC_SYNC BIT(16)
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#define DDR_CTL_SRAM_MISC1_SYNC BIT(15)
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#define DDR_CTL_SRAM_MISC2_SYNC BIT(14)
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#define DDR_CTL_PAD_DDR2_SEL BIT(6)
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#define DDR_CTL_HALF_WIDTH BIT(1)
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#define DDR_CTL_CONFIG_VAL (DDR_CTL_SRAM_TSEL | \
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DDR_CTL_SRAM_GE0_SYNC | \
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DDR_CTL_SRAM_GE1_SYNC | \
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DDR_CTL_SRAM_USB_SYNC | \
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DDR_CTL_SRAM_PCIE_SYNC | \
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DDR_CTL_SRAM_WMAC_SYNC | \
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DDR_CTL_HALF_WIDTH)
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#define DDR_BURST_GE0_MAX_BL_S 0
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#define DDR_BURST_GE0_MAX_BL_M 0xf
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#define DDR_BURST_GE0_MAX_BL(x) \
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(((x) & DDR_BURST_GE0_MAX_BL_M) << DDR_BURST_GE0_MAX_BL_S)
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#define DDR_BURST_GE1_MAX_BL_S 4
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#define DDR_BURST_GE1_MAX_BL_M 0xf
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#define DDR_BURST_GE1_MAX_BL(x) \
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(((x) & DDR_BURST_GE1_MAX_BL_M) << DDR_BURST_GE1_MAX_BL_S)
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#define DDR_BURST_PCIE_MAX_BL_S 8
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#define DDR_BURST_PCIE_MAX_BL_M 0xf
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#define DDR_BURST_PCIE_MAX_BL(x) \
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(((x) & DDR_BURST_PCIE_MAX_BL_M) << DDR_BURST_PCIE_MAX_BL_S)
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#define DDR_BURST_USB_MAX_BL_S 12
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#define DDR_BURST_USB_MAX_BL_M 0xf
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#define DDR_BURST_USB_MAX_BL(x) \
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(((x) & DDR_BURST_USB_MAX_BL_M) << DDR_BURST_USB_MAX_BL_S)
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#define DDR_BURST_CPU_MAX_BL_S 16
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#define DDR_BURST_CPU_MAX_BL_M 0xf
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#define DDR_BURST_CPU_MAX_BL(x) \
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(((x) & DDR_BURST_CPU_MAX_BL_M) << DDR_BURST_CPU_MAX_BL_S)
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#define DDR_BURST_RD_MAX_BL_S 20
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#define DDR_BURST_RD_MAX_BL_M 0xf
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#define DDR_BURST_RD_MAX_BL(x) \
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(((x) & DDR_BURST_RD_MAX_BL_M) << DDR_BURST_RD_MAX_BL_S)
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#define DDR_BURST_WR_MAX_BL_S 24
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#define DDR_BURST_WR_MAX_BL_M 0xf
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#define DDR_BURST_WR_MAX_BL(x) \
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(((x) & DDR_BURST_WR_MAX_BL_M) << DDR_BURST_WR_MAX_BL_S)
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#define DDR_BURST_RWP_MASK_EN_S 28
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#define DDR_BURST_RWP_MASK_EN_M 0x3
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#define DDR_BURST_RWP_MASK_EN(x) \
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(((x) & DDR_BURST_RWP_MASK_EN_M) << DDR_BURST_RWP_MASK_EN_S)
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#define DDR_BURST_CPU_PRI_BE BIT(30)
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#define DDR_BURST_CPU_PRI BIT(31)
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#define DDR_BURST_VAL (DDR_BURST_CPU_PRI_BE | \
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DDR_BURST_RWP_MASK_EN(3) | \
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DDR_BURST_WR_MAX_BL(4) | \
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DDR_BURST_RD_MAX_BL(4) | \
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DDR_BURST_CPU_MAX_BL(4) | \
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DDR_BURST_USB_MAX_BL(4) | \
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DDR_BURST_PCIE_MAX_BL(4) | \
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DDR_BURST_GE1_MAX_BL(4) | \
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DDR_BURST_GE0_MAX_BL(4))
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#define DDR_BURST_WMAC_MAX_BL_S 0
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#define DDR_BURST_WMAC_MAX_BL_M 0xf
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#define DDR_BURST_WMAC_MAX_BL(x) \
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(((x) & DDR_BURST_WMAC_MAX_BL_M) << DDR_BURST_WMAC_MAX_BL_S)
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#define DDR_BURST2_VAL DDR_BURST_WMAC_MAX_BL(4)
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#define DDR2_CONF_TWL_S 10
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#define DDR2_CONF_TWL_M 0xf
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#define DDR2_CONF_TWL(x) \
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(((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
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#define DDR2_CONF_ODT BIT(9)
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#define DDR2_CONF_TFAW_S 2
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#define DDR2_CONF_TFAW_M 0x3f
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#define DDR2_CONF_TFAW(x) \
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(((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
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#define DDR2_CONF_EN BIT(0)
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#define DDR2_CONF_VAL (DDR2_CONF_TWL(5) | \
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DDR2_CONF_TFAW(31) | \
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DDR2_CONF_ODT | \
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DDR2_CONF_EN)
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#define DDR1_EXT_MODE_VAL 0
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#define DDR2_EXT_MODE_VAL 0x402
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#define DDR2_EXT_MODE_OCD_VAL 0x782
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#define DDR1_MODE_DLL_VAL 0x133
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#define DDR2_MODE_DLL_VAL 0x143
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#define DDR1_MODE_VAL 0x33
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#define DDR2_MODE_VAL 0x43
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#define DDR1_TAP_VAL 0x20
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#define DDR2_TAP_VAL 0x10
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#define DDR_REG_BIST_MASK_ADDR_0 0x2c
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#define DDR_REG_BIST_MASK_ADDR_1 0x30
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#define DDR_REG_BIST_MASK_AHB_GE0_0 0x34
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#define DDR_REG_BIST_COMP_AHB_GE0_0 0x38
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#define DDR_REG_BIST_MASK_AHB_GE1_0 0x3c
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#define DDR_REG_BIST_COMP_AHB_GE1_0 0x40
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#define DDR_REG_BIST_COMP_ADDR_0 0x64
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#define DDR_REG_BIST_COMP_ADDR_1 0x68
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#define DDR_REG_BIST_MASK_AHB_GE0_1 0x6c
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#define DDR_REG_BIST_COMP_AHB_GE0_1 0x70
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#define DDR_REG_BIST_MASK_AHB_GE1_1 0x74
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#define DDR_REG_BIST_COMP_AHB_GE1_1 0x78
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#define DDR_REG_BIST 0x11c
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#define DDR_REG_BIST_STATUS 0x120
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#define DDR_BIST_COMP_CNT_S 1
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#define DDR_BIST_COMP_CNT_M 0xff
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#define DDR_BIST_COMP_CNT(x) \
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(((x) & DDR_BIST_COMP_CNT_M) << DDR_BIST_COMP_CNT_S)
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#define DDR_BIST_COMP_CNT_MASK \
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(DDR_BIST_COMP_CNT_M << DDR_BIST_COMP_CNT_S)
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#define DDR_BIST_TEST_START BIT(0)
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#define DDR_BIST_STATUS_DONE BIT(0)
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/* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */
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#define DDR_BIST_MASK_ADDR_VAL 0xfa5de83f
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#define DDR_TAP_MAGIC_VAL 0xaa55aa55
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#define DDR_TAP_MAX_VAL 0x40
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void ddr_init(void)
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{
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void __iomem *regs;
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u32 val;
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regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
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MAP_NOCACHE);
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val = ath79_get_bootstrap();
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if (val & QCA953X_BOOTSTRAP_DDR1) {
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writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
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udelay(10);
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/* For 16-bit DDR */
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writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
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udelay(100);
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/* Burst size */
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writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
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udelay(100);
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writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
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udelay(100);
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/* AHB maximum timeout */
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writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
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udelay(100);
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/* DRAM timing */
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writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
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udelay(100);
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writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
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udelay(100);
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writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
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udelay(100);
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/* Precharge All */
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writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* ODT disable, Full strength, Enable DLL */
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writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
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udelay(100);
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/* Update Extended Mode Register Set (EMRS) */
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writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* Reset DLL, CAS Latency 3, Burst Length 8 */
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writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
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udelay(100);
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/* Update Mode Register Set (MRS) */
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writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* Precharge All */
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writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* Auto Refresh */
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writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* Normal DLL, CAS Latency 3, Burst Length 8 */
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writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
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udelay(100);
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/* Update Mode Register Set (MRS) */
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writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* Refresh time control */
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writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
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udelay(100);
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/* DQS 0 Tap Control */
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writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
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/* DQS 1 Tap Control */
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writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
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} else {
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writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL,
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regs + QCA953X_DDR_REG_CTL_CONF);
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udelay(10);
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/* For 16-bit DDR */
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writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
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udelay(100);
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/* Burst size */
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writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
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udelay(100);
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writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
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udelay(100);
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/* AHB maximum timeout */
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writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
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udelay(100);
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/* DRAM timing */
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writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
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udelay(100);
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writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
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udelay(100);
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writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
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udelay(100);
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/* Enable DDR2 */
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writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG);
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udelay(100);
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/* Precharge All */
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writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* Update Extended Mode Register 2 Set (EMR2S) */
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writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* Update Extended Mode Register 3 Set (EMR3S) */
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writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* 150 ohm, Reduced strength, Enable DLL */
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writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
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udelay(100);
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/* Update Extended Mode Register Set (EMRS) */
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writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* Reset DLL, CAS Latency 4, Burst Length 8 */
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writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
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udelay(100);
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/* Update Mode Register Set (MRS) */
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writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
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udelay(100);
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/* Precharge All */
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writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
|
|
udelay(100);
|
|
|
|
/* Auto Refresh */
|
|
writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
|
|
udelay(100);
|
|
writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
|
|
udelay(100);
|
|
|
|
/* Normal DLL, CAS Latency 4, Burst Length 8 */
|
|
writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
|
|
udelay(100);
|
|
|
|
/* Mode Register Set (MRS) */
|
|
writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
|
|
udelay(100);
|
|
|
|
/* Enable OCD, Enable DLL, Reduced Drive Strength */
|
|
writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
|
|
udelay(100);
|
|
|
|
/* Update Extended Mode Register Set (EMRS) */
|
|
writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
|
|
udelay(100);
|
|
|
|
/* OCD diable, Enable DLL, Reduced Drive Strength */
|
|
writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
|
|
udelay(100);
|
|
|
|
/* Update Extended Mode Register Set (EMRS) */
|
|
writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
|
|
udelay(100);
|
|
|
|
/* Refresh time control */
|
|
writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
|
|
udelay(100);
|
|
|
|
/* DQS 0 Tap Control */
|
|
writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
|
|
|
|
/* DQS 1 Tap Control */
|
|
writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
|
|
}
|
|
}
|
|
|
|
void ddr_tap_tuning(void)
|
|
{
|
|
void __iomem *regs;
|
|
u32 val, pass, tap, cnt, tap_val, last, first;
|
|
|
|
regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
|
|
MAP_NOCACHE);
|
|
|
|
tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
|
|
first = DDR_TAP_MAGIC_VAL;
|
|
last = 0;
|
|
cnt = 0;
|
|
tap = 0;
|
|
|
|
do {
|
|
writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0);
|
|
writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1);
|
|
|
|
writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1);
|
|
writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0);
|
|
writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1);
|
|
writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0);
|
|
writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1);
|
|
writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0);
|
|
writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1);
|
|
writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0);
|
|
writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1);
|
|
writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0);
|
|
|
|
/* Start BIST test */
|
|
writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST);
|
|
|
|
do {
|
|
val = readl(regs + DDR_REG_BIST_STATUS);
|
|
} while (!(val & DDR_BIST_STATUS_DONE));
|
|
|
|
/* Stop BIST test */
|
|
writel(0, regs + DDR_REG_BIST);
|
|
|
|
pass = val & DDR_BIST_COMP_CNT_MASK;
|
|
pass ^= DDR_BIST_COMP_CNT(8);
|
|
if (!pass) {
|
|
if (first != DDR_TAP_MAGIC_VAL) {
|
|
last = tap;
|
|
} else {
|
|
first = tap;
|
|
last = tap;
|
|
}
|
|
cnt++;
|
|
}
|
|
tap++;
|
|
} while (tap < DDR_TAP_MAX_VAL);
|
|
|
|
if (cnt) {
|
|
tap_val = (first + last) / 2;
|
|
tap_val %= DDR_TAP_MAX_VAL;
|
|
}
|
|
|
|
writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0);
|
|
writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1);
|
|
}
|