mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
677 lines
13 KiB
ArmAsm
677 lines
13 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2008 - 2013 Tensilica Inc.
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* (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
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*/
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#include <config.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheasm.h>
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#include <asm/regs.h>
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#include <asm/arch/tie.h>
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#include <asm-offsets.h>
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/*
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* Offsets into the the pt_regs struture.
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* Make sure these always match with the structure defined in ptrace.h!
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*/
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#define PT_PC 0
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#define PT_PS 4
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#define PT_DEPC 8
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#define PT_EXCCAUSE 12
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#define PT_EXCVADDR 16
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#define PT_DEBUGCAUSE 20
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#define PT_WMASK 24
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#define PT_LBEG 28
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#define PT_LEND 32
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#define PT_LCOUNT 36
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#define PT_SAR 40
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#define PT_WINDOWBASE 44
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#define PT_WINDOWSTART 48
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#define PT_SYSCALL 52
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#define PT_ICOUNTLEVEL 56
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#define PT_RESERVED 60
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#define PT_AREG 64
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#define PT_SIZE (64 + 64)
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/*
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* Cache attributes are different for full MMU and region protection.
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*/
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#if XCHAL_HAVE_PTP_MMU
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#define CA_WRITEBACK (0x7)
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#else
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#define CA_WRITEBACK (0x4)
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#endif
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/*
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* Reset vector.
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* Only a trampoline to jump to _start
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* (Note that we have to mark the section writable as the section contains
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* a relocatable literal)
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*/
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.section .ResetVector.text, "awx"
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.global _ResetVector
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_ResetVector:
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j 1f
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.align 4
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2: .long _start
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1: l32r a2, 2b
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jx a2
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/*
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* Processor initialization. We still run in rom space.
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*
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* NOTE: Running in ROM
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* For Xtensa, we currently don't allow to run some code from ROM but
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* unpack the data immediately to memory. This requires, for example,
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* that DDR has been set up before running U-Boot. (See also comments
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* inline for ways to change it)
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*/
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.section .reset.text, "ax"
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.global _start
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.align 4
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_start:
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/* Keep a0 = 0 for various initializations */
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movi a0, 0
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/*
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* For full MMU cores, put page table at unmapped virtual address.
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* This ensures that accesses outside the static maps result
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* in miss exceptions rather than random behaviour.
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*/
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#if XCHAL_HAVE_PTP_MMU
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wsr a0, PTEVADDR
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#endif
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/* Disable dbreak debug exceptions */
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#if XCHAL_HAVE_DEBUG && XCHAL_NUM_DBREAK > 0
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.set _index, 0
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.rept XCHAL_NUM_DBREAK
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wsr a0, DBREAKC + _index
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.set _index, _index + 1
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.endr
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#endif
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/* Reset windowbase and windowstart */
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#if XCHAL_HAVE_WINDOWED
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movi a3, 1
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wsr a3, windowstart
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wsr a0, windowbase
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rsync
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movi a0, 0 /* windowbase might have changed */
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#endif
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/*
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* Vecbase in bitstream may differ from header files
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* set or check it.
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*/
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#if XCHAL_HAVE_VECBASE
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movi a3, XCHAL_VECBASE_RESET_VADDR /* VECBASE reset value */
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wsr a3, VECBASE
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#endif
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#if XCHAL_HAVE_LOOPS
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/* Disable loops */
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wsr a0, LCOUNT
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#endif
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/* Set PS.WOE = 0, PS.EXCM = 0 (for loop), PS.INTLEVEL = EXCM level */
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#if XCHAL_HAVE_XEA1
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movi a2, 1
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#else
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movi a2, XCHAL_EXCM_LEVEL
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#endif
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wsr a2, PS
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rsync
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/* Unlock and invalidate caches */
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___unlock_dcache_all a2, a3
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___invalidate_dcache_all a2, a3
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___unlock_icache_all a2, a3
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___invalidate_icache_all a2, a3
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isync
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/* Unpack data sections */
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movi a2, __reloc_table_start
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movi a3, __reloc_table_end
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1: beq a2, a3, 3f # no more entries?
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l32i a4, a2, 0 # start destination (in RAM)
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l32i a5, a2, 4 # end destination (in RAM)
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l32i a6, a2, 8 # start source (in ROM)
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addi a2, a2, 12 # next entry
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beq a4, a5, 1b # skip, empty entry
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beq a4, a6, 1b # skip, source and destination are the same
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/* If there's memory protection option with 512MB TLB regions and
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* cache attributes in TLB entries and caching is not inhibited,
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* enable data/instruction cache for relocated image.
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*/
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#if XCHAL_HAVE_SPANNING_WAY && \
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(!defined(CONFIG_SYS_DCACHE_OFF) || \
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!defined(CONFIG_SYS_ICACHE_OFF))
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srli a7, a4, 29
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slli a7, a7, 29
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addi a7, a7, XCHAL_SPANNING_WAY
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#ifndef CONFIG_SYS_DCACHE_OFF
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rdtlb1 a8, a7
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srli a8, a8, 4
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slli a8, a8, 4
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addi a8, a8, CA_WRITEBACK
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wdtlb a8, a7
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#endif
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#ifndef CONFIG_SYS_ICACHE_OFF
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ritlb1 a8, a7
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srli a8, a8, 4
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slli a8, a8, 4
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addi a8, a8, CA_WRITEBACK
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witlb a8, a7
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#endif
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isync
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#endif
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2: l32i a7, a6, 0
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addi a6, a6, 4
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s32i a7, a4, 0
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addi a4, a4, 4
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bltu a4, a5, 2b
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j 1b
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3: /* All code and initalized data segments have been copied */
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/* Setup PS, PS.WOE = 1, PS.EXCM = 0, PS.INTLEVEL = EXCM level. */
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#if __XTENSA_CALL0_ABI__
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movi a2, XCHAL_EXCM_LEVEL
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#else
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movi a2, (1<<PS_WOE_BIT) | XCHAL_EXCM_LEVEL
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#endif
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wsr a2, PS
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rsync
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/* Writeback */
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___flush_dcache_all a2, a3
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#ifdef __XTENSA_WINDOWED_ABI__
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/*
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* In windowed ABI caller and call target need to be within the same
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* gigabyte. Put the rest of the code into the text segment and jump
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* there.
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*/
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movi a4, .Lboard_init_code
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jx a4
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.text
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.align 4
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.Lboard_init_code:
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#endif
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movi a0, 0
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movi sp, (XTENSA_SYS_TEXT_ADDR - 16) & 0xfffffff0
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#ifdef CONFIG_DEBUG_UART
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movi a4, debug_uart_init
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#ifdef __XTENSA_CALL0_ABI__
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callx0 a4
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#else
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callx4 a4
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#endif
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#endif
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movi a4, board_init_f_alloc_reserve
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#ifdef __XTENSA_CALL0_ABI__
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mov a2, sp
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callx0 a4
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mov sp, a2
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#else
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mov a6, sp
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callx4 a4
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movsp sp, a6
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#endif
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movi a4, board_init_f_init_reserve
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#ifdef __XTENSA_CALL0_ABI__
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callx0 a4
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#else
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callx4 a4
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#endif
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/*
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* Call board initialization routine (never returns).
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*/
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movi a4, board_init_f
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#ifdef __XTENSA_CALL0_ABI__
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movi a2, 0
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callx0 a4
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#else
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movi a6, 0
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callx4 a4
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#endif
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/* Never Returns */
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ill
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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* a2 = addr_sp
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* a3 = gd
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* a4 = destination address
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*/
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.text
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.globl relocate_code
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.align 4
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relocate_code:
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abi_entry
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#ifdef __XTENSA_CALL0_ABI__
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mov a1, a2
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mov a2, a3
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mov a3, a4
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movi a0, board_init_r
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callx0 a0
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#else
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/* We can't movsp here, because the chain of stack frames may cross
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* the now reserved memory. We need to toss all window frames except
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* the current, create new pristine stack frame and start from scratch.
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*/
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rsr a0, windowbase
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ssl a0
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movi a0, 1
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sll a0, a0
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wsr a0, windowstart
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rsync
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movi a0, 0
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/* Reserve 16-byte save area */
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addi sp, a2, -16
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mov a6, a3
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mov a7, a4
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movi a4, board_init_r
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callx4 a4
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#endif
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ill
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#if XCHAL_HAVE_EXCEPTIONS
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/*
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* Exception vectors.
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*
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* Various notes:
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* - We currently don't use the user exception vector (PS.UM is always 0),
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* but do define such a vector, just in case. They both jump to the
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* same exception handler, though.
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* - We currently only save the bare minimum number of registers:
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* a0...a15, sar, loop-registers, exception register (epc1, excvaddr,
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* exccause, depc)
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* - WINDOWSTART is only saved to identify if registers have been spilled
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* to the wrong stack (exception stack) while executing the exception
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* handler.
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*/
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.section .KernelExceptionVector.text, "ax"
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.global _KernelExceptionVector
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_KernelExceptionVector:
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wsr a2, EXCSAVE1
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movi a2, ExceptionHandler
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jx a2
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.section .UserExceptionVector.text, "ax"
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.global _UserExceptionVector
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_UserExceptionVector:
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wsr a2, EXCSAVE1
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movi a2, ExceptionHandler
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jx a2
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#if !XCHAL_HAVE_XEA1
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.section .DoubleExceptionVector.text, "ax"
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.global _DoubleExceptionVector
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_DoubleExceptionVector:
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#ifdef __XTENSA_CALL0_ABI__
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wsr a0, EXCSAVE1
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movi a0, hang # report and ask user to reset board
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callx0 a0
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#else
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wsr a4, EXCSAVE1
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movi a4, hang # report and ask user to reset board
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callx4 a4
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#endif
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#endif
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/* Does not return here */
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.text
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.align 4
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ExceptionHandler:
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rsr a2, EXCCAUSE # find handler
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#if XCHAL_HAVE_WINDOWED
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/* Special case for alloca handler */
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bnei a2, 5, 1f # jump if not alloca exception
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addi a1, a1, -16 - 4 # create a small stack frame
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s32i a3, a1, 0 # and save a3 (a2 still in excsave1)
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movi a2, fast_alloca_exception
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jx a2 # jump to fast_alloca_exception
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#endif
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/* All other exceptions go here: */
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/* Create ptrace stack and save a0...a3 */
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1: addi a2, a1, - PT_SIZE - 16
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s32i a0, a2, PT_AREG + 0 * 4
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s32i a1, a2, PT_AREG + 1 * 4
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s32i a3, a2, PT_AREG + 3 * 4
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rsr a3, EXCSAVE1
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s32i a3, a2, PT_AREG + 2 * 4
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mov a1, a2
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/* Save remaining AR registers */
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s32i a4, a1, PT_AREG + 4 * 4
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s32i a5, a1, PT_AREG + 5 * 4
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s32i a6, a1, PT_AREG + 6 * 4
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s32i a7, a1, PT_AREG + 7 * 4
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s32i a8, a1, PT_AREG + 8 * 4
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s32i a9, a1, PT_AREG + 9 * 4
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s32i a10, a1, PT_AREG + 10 * 4
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s32i a11, a1, PT_AREG + 11 * 4
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s32i a12, a1, PT_AREG + 12 * 4
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s32i a13, a1, PT_AREG + 13 * 4
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s32i a14, a1, PT_AREG + 14 * 4
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s32i a15, a1, PT_AREG + 15 * 4
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/* Save SRs */
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#if XCHAL_HAVE_WINDOWED
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rsr a2, WINDOWSTART
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s32i a2, a1, PT_WINDOWSTART
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#endif
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rsr a2, SAR
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rsr a3, EPC1
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rsr a4, EXCVADDR
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s32i a2, a1, PT_SAR
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s32i a3, a1, PT_PC
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s32i a4, a1, PT_EXCVADDR
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#if XCHAL_HAVE_LOOPS
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movi a2, 0
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rsr a3, LBEG
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xsr a2, LCOUNT
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s32i a3, a1, PT_LBEG
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rsr a3, LEND
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s32i a2, a1, PT_LCOUNT
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s32i a3, a1, PT_LEND
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#endif
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/* Set up C environment and call registered handler */
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/* Setup stack, PS.WOE = 1, PS.EXCM = 0, PS.INTLEVEL = EXCM level. */
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rsr a2, EXCCAUSE
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#if XCHAL_HAVE_XEA1
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movi a3, (1<<PS_WOE_BIT) | 1
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#elif __XTENSA_CALL0_ABI__
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movi a3, XCHAL_EXCM_LEVEL
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#else
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movi a3, (1<<PS_WOE_BIT) | XCHAL_EXCM_LEVEL
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#endif
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xsr a3, PS
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rsync
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s32i a2, a1, PT_EXCCAUSE
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s32i a3, a1, PT_PS
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movi a0, exc_table
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addx4 a0, a2, a0
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l32i a0, a0, 0
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#ifdef __XTENSA_CALL0_ABI__
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mov a2, a1 # Provide stack frame as only argument
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callx0 a0
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l32i a3, a1, PT_PS
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#else
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mov a6, a1 # Provide stack frame as only argument
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callx4 a0
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#endif
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/* Restore PS and go to exception mode (PS.EXCM=1) */
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wsr a3, PS
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/* Restore SR registers */
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#if XCHAL_HAVE_LOOPS
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l32i a2, a1, PT_LBEG
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l32i a3, a1, PT_LEND
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l32i a4, a1, PT_LCOUNT
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wsr a2, LBEG
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wsr a3, LEND
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wsr a4, LCOUNT
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#endif
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l32i a2, a1, PT_SAR
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l32i a3, a1, PT_PC
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wsr a2, SAR
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wsr a3, EPC1
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#if XCHAL_HAVE_WINDOWED
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/* Do we need to simulate a MOVSP? */
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l32i a2, a1, PT_WINDOWSTART
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addi a3, a2, -1
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and a2, a2, a3
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beqz a2, 1f # Skip if regs were spilled before exc.
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rsr a2, WINDOWSTART
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addi a3, a2, -1
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and a2, a2, a3
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bnez a2, 1f # Skip if registers aren't spilled now
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addi a2, a1, -16
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l32i a4, a2, 0
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l32i a5, a2, 4
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s32i a4, a1, PT_SIZE + 0
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s32i a5, a1, PT_SIZE + 4
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l32i a4, a2, 8
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l32i a5, a2, 12
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s32i a4, a1, PT_SIZE + 8
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s32i a5, a1, PT_SIZE + 12
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#endif
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/* Restore address register */
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1: l32i a15, a1, PT_AREG + 15 * 4
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l32i a14, a1, PT_AREG + 14 * 4
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l32i a13, a1, PT_AREG + 13 * 4
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l32i a12, a1, PT_AREG + 12 * 4
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l32i a11, a1, PT_AREG + 11 * 4
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l32i a10, a1, PT_AREG + 10 * 4
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l32i a9, a1, PT_AREG + 9 * 4
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l32i a8, a1, PT_AREG + 8 * 4
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l32i a7, a1, PT_AREG + 7 * 4
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l32i a6, a1, PT_AREG + 6 * 4
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l32i a5, a1, PT_AREG + 5 * 4
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l32i a4, a1, PT_AREG + 4 * 4
|
|
l32i a3, a1, PT_AREG + 3 * 4
|
|
l32i a2, a1, PT_AREG + 2 * 4
|
|
l32i a0, a1, PT_AREG + 0 * 4
|
|
|
|
l32i a1, a1, PT_AREG + 1 * 4 # Remove ptrace stack frame
|
|
|
|
rfe
|
|
|
|
#endif /* XCHAL_HAVE_EXCEPTIONS */
|
|
|
|
#if XCHAL_HAVE_WINDOWED
|
|
|
|
/*
|
|
* Window overflow and underflow handlers.
|
|
* The handlers must be 64 bytes apart, first starting with the underflow
|
|
* handlers underflow-4 to underflow-12, then the overflow handlers
|
|
* overflow-4 to overflow-12.
|
|
*
|
|
* Note: We rerun the underflow handlers if we hit an exception, so
|
|
* we try to access any page that would cause a page fault early.
|
|
*/
|
|
|
|
.section .WindowVectors.text, "ax"
|
|
|
|
/* 4-Register Window Overflow Vector (Handler) */
|
|
|
|
.align 64
|
|
.global _WindowOverflow4
|
|
_WindowOverflow4:
|
|
s32e a0, a5, -16
|
|
s32e a1, a5, -12
|
|
s32e a2, a5, -8
|
|
s32e a3, a5, -4
|
|
rfwo
|
|
|
|
|
|
/* 4-Register Window Underflow Vector (Handler) */
|
|
|
|
.align 64
|
|
.global _WindowUnderflow4
|
|
_WindowUnderflow4:
|
|
l32e a0, a5, -16
|
|
l32e a1, a5, -12
|
|
l32e a2, a5, -8
|
|
l32e a3, a5, -4
|
|
rfwu
|
|
|
|
/*
|
|
* a0: a0
|
|
* a1: new stack pointer = a1 - 16 - 4
|
|
* a2: available, saved in excsave1
|
|
* a3: available, saved on stack *a1
|
|
*/
|
|
|
|
/* 15*/ .byte 0xff
|
|
|
|
fast_alloca_exception: /* must be at _WindowUnderflow4 + 16 */
|
|
|
|
/* 16*/ rsr a2, PS
|
|
/* 19*/ rsr a3, WINDOWBASE
|
|
/* 22*/ extui a2, a2, PS_OWB_SHIFT, PS_OWB_SHIFT
|
|
/* 25*/ xor a2, a2, a3
|
|
/* 28*/ rsr a3, PS
|
|
/* 31*/ slli a2, a2, PS_OWB_SHIFT
|
|
/* 34*/ xor a2, a3, a2
|
|
/* 37*/ wsr a2, PS
|
|
|
|
/* 40*/ _l32i a3, a1, 0
|
|
/* 43*/ addi a1, a1, 16 + 4
|
|
/* 46*/ rsr a2, EXCSAVE1
|
|
|
|
/* 49*/ rotw -1
|
|
/* 52*/ _bbci.l a4, 31, _WindowUnderflow4 /* 0x: call4 */
|
|
/* 55*/ rotw -1
|
|
/* 58*/ _bbci.l a8, 30, _WindowUnderflow8 /* 10: call8 */
|
|
/* 61*/ _j __WindowUnderflow12 /* 11: call12 */
|
|
/* 64*/
|
|
|
|
/* 8-Register Window Overflow Vector (Handler) */
|
|
|
|
.align 64
|
|
.global _WindowOverflow8
|
|
_WindowOverflow8:
|
|
s32e a0, a9, -16
|
|
l32e a0, a1, -12
|
|
s32e a2, a9, -8
|
|
s32e a1, a9, -12
|
|
s32e a3, a9, -4
|
|
s32e a4, a0, -32
|
|
s32e a5, a0, -28
|
|
s32e a6, a0, -24
|
|
s32e a7, a0, -20
|
|
rfwo
|
|
|
|
/* 8-Register Window Underflow Vector (Handler) */
|
|
|
|
.align 64
|
|
.global _WindowUnderflow8
|
|
_WindowUnderflow8:
|
|
l32e a1, a9, -12
|
|
l32e a0, a9, -16
|
|
l32e a7, a1, -12
|
|
l32e a2, a9, -8
|
|
l32e a4, a7, -32
|
|
l32e a3, a9, -4
|
|
l32e a5, a7, -28
|
|
l32e a6, a7, -24
|
|
l32e a7, a7, -20
|
|
rfwu
|
|
|
|
/* 12-Register Window Overflow Vector (Handler) */
|
|
|
|
.align 64
|
|
.global _WindowOverflow12
|
|
_WindowOverflow12:
|
|
s32e a0, a13, -16
|
|
l32e a0, a1, -12
|
|
s32e a1, a13, -12
|
|
s32e a2, a13, -8
|
|
s32e a3, a13, -4
|
|
s32e a4, a0, -48
|
|
s32e a5, a0, -44
|
|
s32e a6, a0, -40
|
|
s32e a7, a0, -36
|
|
s32e a8, a0, -32
|
|
s32e a9, a0, -28
|
|
s32e a10, a0, -24
|
|
s32e a11, a0, -20
|
|
rfwo
|
|
|
|
/* 12-Register Window Underflow Vector (Handler) */
|
|
|
|
.org _WindowOverflow12 + 64 - 3
|
|
__WindowUnderflow12:
|
|
rotw -1
|
|
.global _WindowUnderflow12
|
|
_WindowUnderflow12:
|
|
l32e a1, a13, -12
|
|
l32e a0, a13, -16
|
|
l32e a11, a1, -12
|
|
l32e a2, a13, -8
|
|
l32e a4, a11, -48
|
|
l32e a8, a11, -32
|
|
l32e a3, a13, -4
|
|
l32e a5, a11, -44
|
|
l32e a6, a11, -40
|
|
l32e a7, a11, -36
|
|
l32e a9, a11, -28
|
|
l32e a10, a11, -24
|
|
l32e a11, a11, -20
|
|
rfwu
|
|
|
|
#endif /* XCHAL_HAVE_WINDOWED */
|