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https://github.com/brain-hackers/u-boot-brain
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72c347ced8
Add optional "mask" argument to the SoCFPGA bridge command, to select which bridges should be enabled/disabled. This allows the user to avoid enabling bridges which are not connected into the FPGA fabric. Default behavior is to enable/disable all bridges. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
161 lines
3.5 KiB
C
161 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <altera.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <watchdog.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/nic301.h>
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#include <asm/arch/scu.h>
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#include <asm/pl310.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SYS_L2_PL310
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static const struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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#endif
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struct bsel bsel_str[] = {
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{ "rsvd", "Reserved", },
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{ "fpga", "FPGA (HPS2FPGA Bridge)", },
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{ "nand", "NAND Flash (1.8V)", },
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{ "nand", "NAND Flash (3.0V)", },
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{ "sd", "SD/MMC External Transceiver (1.8V)", },
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{ "sd", "SD/MMC Internal Transceiver (3.0V)", },
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{ "qspi", "QSPI Flash (1.8V)", },
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{ "qspi", "QSPI Flash (3.0V)", },
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};
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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icache_enable();
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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dcache_enable();
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#endif
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}
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#ifdef CONFIG_SYS_L2_PL310
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void v7_outer_cache_enable(void)
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{
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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writel(0x0, &pl310->pl310_tag_latency_ctrl);
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writel(0x10, &pl310->pl310_data_latency_ctrl);
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/* enable BRESP, instruction and data prefetch, full line of zeroes */
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setbits_le32(&pl310->pl310_aux_ctrl,
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L310_AUX_CTRL_DATA_PREFETCH_MASK |
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L310_AUX_CTRL_INST_PREFETCH_MASK |
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L310_SHARED_ATT_OVERRIDE_ENABLE);
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/* Enable the L2 cache */
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setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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void v7_outer_cache_disable(void)
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{
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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#endif
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#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
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defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
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int overwrite_console(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_FPGA
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/* add device descriptor to FPGA device table */
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void socfpga_fpga_add(void *fpga_desc)
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{
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fpga_init();
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fpga_add(fpga_altera, fpga_desc);
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}
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#endif
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_HW_WATCHDOG
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/*
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* In case the watchdog is enabled, make sure to (re-)configure it
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* so that the defined timeout is valid. Otherwise the SPL (Perloader)
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* timeout value is still active which might too short for Linux
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* booting.
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*/
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hw_watchdog_init();
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#else
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/*
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* If the HW watchdog is NOT enabled, make sure it is not running,
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* for example because it was enabled in the preloader. This might
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* trigger a watchdog-triggered reboot of Linux kernel later.
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* Toggle watchdog reset, so watchdog in not running state.
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*/
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
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#endif
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned int mask = ~0;
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if (argc < 2 || argc > 3)
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return CMD_RET_USAGE;
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argv++;
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if (argc == 3)
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mask = simple_strtoul(argv[1], NULL, 16);
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switch (*argv[0]) {
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case 'e': /* Enable */
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do_bridge_reset(1, mask);
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break;
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case 'd': /* Disable */
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do_bridge_reset(0, mask);
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break;
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default:
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return CMD_RET_USAGE;
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}
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return 0;
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}
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U_BOOT_CMD(bridge, 3, 1, do_bridge,
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"SoCFPGA HPS FPGA bridge control",
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"enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
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"bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
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""
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);
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#endif
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