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72a9414bd4
For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement. We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM, the NUM should always be less than the DENOM. So our setting violates the rule. Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock is 318.9888Mhz, which also meet the DDR requirement. To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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| .. | ||
| imximage.cfg | ||
| Kconfig | ||
| MAINTAINERS | ||
| Makefile | ||
| mx7ulp_evk.c | ||
| plugin.S | ||