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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
729c1fe656
When flush_cache() is called during boot on our ~7M kernel image, the hundreds of thousands of WATCHDOG_RESET calls end up adding significantly to boottime. Flushing a single cache line doesn't take many microseconds, so doing these calls for every cache line is complete overkill. The generic watchdog_reset() provided by wdt-uclass.c actually contains some rate-limiting logic that should in theory mitigate this, but alas, that rate-limiting must be disabled on powerpc because of its get_timer() implementation - get_timer() works just fine until interrupts are disabled, but it just so happens that the "big" flush_cache() call happens in the part of bootm where interrupts are indeed disabled. [1] [2] [3] I have checked with objdump that the generated code doesn't change when this option is left at its default value of 0: gcc is smart enough to see that the ">=" comparison is tautologically true, hence all assignments to "flushed" are eliminated as dead stores. On our board, setting the option to something like 65536 ends up reducing total boottime by about 0.8 seconds. [1] https://patchwork.ozlabs.org/project/uboot/patch/20200605111657.28773-1-rasmus.villemoes@prevas.dk/ [2] https://lists.denx.de/pipermail/u-boot/2021-April/446906.html [3] https://lists.denx.de/pipermail/u-boot/2021-April/447280.html Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
55 lines
1005 B
Plaintext
55 lines
1005 B
Plaintext
menu "PowerPC architecture"
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depends on PPC
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config SYS_ARCH
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default "powerpc"
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choice
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prompt "CPU select"
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optional
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config MPC83xx
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bool "MPC83xx"
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select CREATE_ARCH_SYMLINK
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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config MPC85xx
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bool "MPC85xx"
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select CREATE_ARCH_SYMLINK
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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select BINMAN if OF_SEPARATE
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imply CMD_HASH
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imply CMD_IRQ
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imply USB_EHCI_HCD if USB
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config MPC86xx
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bool "MPC86xx"
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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imply CMD_REGINFO
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config MPC8xx
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bool "MPC8xx"
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select BOARD_EARLY_INIT_F
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imply CMD_REGINFO
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imply WDT_MPC8xx
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endchoice
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config HIGH_BATS
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bool "Enable high BAT registers"
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help
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Enable BATs (block address translation registers) 4-7 on machines
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that support them.
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source "arch/powerpc/cpu/mpc83xx/Kconfig"
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source "arch/powerpc/cpu/mpc85xx/Kconfig"
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source "arch/powerpc/cpu/mpc86xx/Kconfig"
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source "arch/powerpc/cpu/mpc8xx/Kconfig"
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source "arch/powerpc/lib/Kconfig"
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endmenu
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