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https://github.com/brain-hackers/u-boot-brain
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![Masahiro Yamada](/assets/img/avatar_default.png)
In Linux, the clock rate of the UART is given by the clock driver. If you try to follow that in U-Boot, you would end up with adding more u-boot,dm-pre-reloc properties, and also the clock driver would be too big for SPL, which is used for UniPhier ARMv7 platform. The current solution is to add 'clock-frequency' property to the UART nodes, but it does not exist in the DT files in Linux. I do not want to let DT diverge for U-Boot. Check the SoC compatible and set the clock rate according to it. This will be helpful to sync DT between Linux and U-Boot. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
174 lines
4.5 KiB
C
174 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2015 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <linux/bug.h>
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#include <linux/io.h>
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#include <linux/serial_reg.h>
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#include <linux/sizes.h>
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#include <linux/errno.h>
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#include <serial.h>
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#include <fdtdec.h>
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/*
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* Note: Register map is slightly different from that of 16550.
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*/
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struct uniphier_serial {
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u32 rx; /* In: Receive buffer */
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#define tx rx /* Out: Transmit buffer */
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u32 ier; /* Interrupt Enable Register */
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u32 iir; /* In: Interrupt ID Register */
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u32 char_fcr; /* Charactor / FIFO Control Register */
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u32 lcr_mcr; /* Line/Modem Control Register */
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#define LCR_SHIFT 8
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#define LCR_MASK (0xff << (LCR_SHIFT))
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u32 lsr; /* In: Line Status Register */
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u32 msr; /* In: Modem Status Register */
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u32 __rsv0;
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u32 __rsv1;
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u32 dlr; /* Divisor Latch Register */
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};
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struct uniphier_serial_priv {
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struct uniphier_serial __iomem *membase;
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unsigned int uartclk;
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};
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#define uniphier_serial_port(dev) \
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((struct uniphier_serial_priv *)dev_get_priv(dev))->membase
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static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct uniphier_serial_priv *priv = dev_get_priv(dev);
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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const unsigned int mode_x_div = 16;
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unsigned int divisor;
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divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate);
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writel(divisor, &port->dlr);
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return 0;
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}
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static int uniphier_serial_getc(struct udevice *dev)
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{
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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if (!(readl(&port->lsr) & UART_LSR_DR))
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return -EAGAIN;
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return readl(&port->rx);
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}
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static int uniphier_serial_putc(struct udevice *dev, const char c)
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{
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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if (!(readl(&port->lsr) & UART_LSR_THRE))
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return -EAGAIN;
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writel(c, &port->tx);
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return 0;
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}
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static int uniphier_serial_pending(struct udevice *dev, bool input)
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{
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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if (input)
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return readl(&port->lsr) & UART_LSR_DR;
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else
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return !(readl(&port->lsr) & UART_LSR_THRE);
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}
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/*
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* SPL does not have enough memory footprint for the clock driver.
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* Hardcode clock frequency for each SoC.
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*/
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struct uniphier_serial_clk_data {
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const char *compatible;
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unsigned int clk_rate;
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};
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static const struct uniphier_serial_clk_data uniphier_serial_clk_data[] = {
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{ .compatible = "socionext,uniphier-ld4", .clk_rate = 36864000 },
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{ .compatible = "socionext,uniphier-pro4", .clk_rate = 73728000 },
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{ .compatible = "socionext,uniphier-sld8", .clk_rate = 80000000 },
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{ .compatible = "socionext,uniphier-pro5", .clk_rate = 73728000 },
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{ .compatible = "socionext,uniphier-pxs2", .clk_rate = 88888888 },
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{ .compatible = "socionext,uniphier-ld6b", .clk_rate = 88888888 },
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{ .compatible = "socionext,uniphier-ld11", .clk_rate = 58823529 },
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{ .compatible = "socionext,uniphier-ld20", .clk_rate = 58823529 },
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{ .compatible = "socionext,uniphier-pxs3", .clk_rate = 58823529 },
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{ /* sentinel */ },
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};
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static int uniphier_serial_probe(struct udevice *dev)
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{
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struct uniphier_serial_priv *priv = dev_get_priv(dev);
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struct uniphier_serial __iomem *port;
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const struct uniphier_serial_clk_data *clk_data;
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ofnode root_node;
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fdt_addr_t base;
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u32 tmp;
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base = devfdt_get_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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port = devm_ioremap(dev, base, SZ_64);
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if (!port)
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return -ENOMEM;
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priv->membase = port;
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root_node = ofnode_path("/");
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clk_data = uniphier_serial_clk_data;
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while (clk_data->compatible) {
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if (ofnode_device_is_compatible(root_node,
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clk_data->compatible))
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break;
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clk_data++;
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}
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if (WARN_ON(!clk_data->compatible))
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return -ENOTSUPP;
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priv->uartclk = clk_data->clk_rate;
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tmp = readl(&port->lcr_mcr);
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tmp &= ~LCR_MASK;
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tmp |= UART_LCR_WLEN8 << LCR_SHIFT;
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writel(tmp, &port->lcr_mcr);
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return 0;
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}
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static const struct udevice_id uniphier_uart_of_match[] = {
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{ .compatible = "socionext,uniphier-uart" },
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{ /* sentinel */ }
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};
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static const struct dm_serial_ops uniphier_serial_ops = {
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.setbrg = uniphier_serial_setbrg,
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.getc = uniphier_serial_getc,
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.putc = uniphier_serial_putc,
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.pending = uniphier_serial_pending,
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};
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U_BOOT_DRIVER(uniphier_serial) = {
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.name = "uniphier-uart",
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.id = UCLASS_SERIAL,
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.of_match = uniphier_uart_of_match,
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.probe = uniphier_serial_probe,
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.priv_auto_alloc_size = sizeof(struct uniphier_serial_priv),
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.ops = &uniphier_serial_ops,
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};
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