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https://github.com/brain-hackers/u-boot-brain
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![Ryder Lee](/assets/img/avatar_default.png)
Many SoCs from MediaTek have a high-speed uart. This UART is compatible with the ns16550 in legacy mode. It has extra registers for high-speed mode which can reach a maximum baudrate at 921600. However this UART will no longer be compatible if it's in high-speed mode. Some BootROM of MediaTek's SoCs will change the UART into high-speed mode and the U-Boot must use this driver to initialize the UART. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Tested-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
268 lines
5.8 KiB
C
268 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek High-speed UART driver
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*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <errno.h>
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#include <serial.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <asm/types.h>
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struct mtk_serial_regs {
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u32 rbr;
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u32 ier;
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u32 fcr;
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u32 lcr;
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u32 mcr;
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u32 lsr;
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u32 msr;
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u32 spr;
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u32 mdr1;
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u32 highspeed;
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u32 sample_count;
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u32 sample_point;
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u32 fracdiv_l;
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u32 fracdiv_m;
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u32 escape_en;
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u32 guard;
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u32 rx_sel;
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};
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#define thr rbr
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#define iir fcr
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#define dll rbr
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#define dlm ier
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#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LSR_DR 0x01 /* Data ready */
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#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
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/* the data is correct if the real baud is within 3%. */
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#define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
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#define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
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struct mtk_serial_priv {
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struct mtk_serial_regs __iomem *regs;
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u32 clock;
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};
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static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
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{
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bool support_clk12m_baud115200;
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u32 quot, samplecount, realbaud;
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if ((baud <= 115200) && (priv->clock == 12000000))
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support_clk12m_baud115200 = true;
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else
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support_clk12m_baud115200 = false;
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if (baud <= 115200) {
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writel(0, &priv->regs->highspeed);
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quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);
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if (support_clk12m_baud115200) {
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writel(3, &priv->regs->highspeed);
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quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
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if (quot == 0)
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quot = 1;
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samplecount = DIV_ROUND_CLOSEST(priv->clock,
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quot * baud);
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if (samplecount != 0) {
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realbaud = priv->clock / samplecount / quot;
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if ((realbaud > BAUD_ALLOW_MAX(baud)) ||
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(realbaud < BAUD_ALLOW_MIX(baud))) {
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pr_info("baud %d can't be handled\n",
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baud);
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}
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} else {
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pr_info("samplecount is 0\n");
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}
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}
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} else if (baud <= 576000) {
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writel(2, &priv->regs->highspeed);
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/* Set to next lower baudrate supported */
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if ((baud == 500000) || (baud == 576000))
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baud = 460800;
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quot = DIV_ROUND_UP(priv->clock, 4 * baud);
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} else {
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writel(3, &priv->regs->highspeed);
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quot = DIV_ROUND_UP(priv->clock, 256 * baud);
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}
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/* set divisor */
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writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr);
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writel(quot & 0xff, &priv->regs->dll);
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writel((quot >> 8) & 0xff, &priv->regs->dlm);
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writel(UART_LCR_WLS_8, &priv->regs->lcr);
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if (baud > 460800) {
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u32 tmp;
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tmp = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
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writel(tmp - 1, &priv->regs->sample_count);
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writel((tmp - 2) >> 1, &priv->regs->sample_point);
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} else {
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writel(0, &priv->regs->sample_count);
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writel(0xff, &priv->regs->sample_point);
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}
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if (support_clk12m_baud115200) {
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writel(samplecount - 1, &priv->regs->sample_count);
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writel((samplecount - 2) >> 1, &priv->regs->sample_point);
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}
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}
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static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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_mtk_serial_setbrg(priv, baudrate);
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return 0;
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}
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static int mtk_serial_putc(struct udevice *dev, const char ch)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
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return -EAGAIN;
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writel(ch, &priv->regs->thr);
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if (ch == '\n')
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WATCHDOG_RESET();
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return 0;
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}
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static int mtk_serial_getc(struct udevice *dev)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
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return -EAGAIN;
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return readl(&priv->regs->rbr);
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}
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static int mtk_serial_pending(struct udevice *dev, bool input)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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if (input)
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return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
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else
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return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
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}
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static int mtk_serial_probe(struct udevice *dev)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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/* Disable interrupt */
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writel(0, &priv->regs->ier);
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return 0;
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}
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static int mtk_serial_ofdata_to_platdata(struct udevice *dev)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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struct clk clk;
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int err;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
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err = clk_get_by_index(dev, 0, &clk);
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if (!err) {
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err = clk_get_rate(&clk);
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if (!IS_ERR_VALUE(err))
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priv->clock = err;
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} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
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debug("mtk_serial: failed to get clock\n");
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return err;
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}
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if (!priv->clock)
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priv->clock = dev_read_u32_default(dev, "clock-frequency", 0);
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if (!priv->clock) {
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debug("mtk_serial: clock not defined\n");
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return -EINVAL;
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}
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return 0;
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}
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static const struct dm_serial_ops mtk_serial_ops = {
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.putc = mtk_serial_putc,
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.pending = mtk_serial_pending,
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.getc = mtk_serial_getc,
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.setbrg = mtk_serial_setbrg,
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};
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static const struct udevice_id mtk_serial_ids[] = {
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{ .compatible = "mediatek,hsuart" },
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{ .compatible = "mediatek,mt6577-uart" },
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{ }
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};
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U_BOOT_DRIVER(serial_mtk) = {
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.name = "serial_mtk",
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.id = UCLASS_SERIAL,
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.of_match = mtk_serial_ids,
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.ofdata_to_platdata = mtk_serial_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct mtk_serial_priv),
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.probe = mtk_serial_probe,
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.ops = &mtk_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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#ifdef CONFIG_DEBUG_UART_MTK
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#include <debug_uart.h>
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static inline void _debug_uart_init(void)
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{
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struct mtk_serial_priv priv;
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priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
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priv.clock = CONFIG_DEBUG_UART_CLOCK;
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writel(0, &priv.regs->ier);
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_mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
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}
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static inline void _debug_uart_putc(int ch)
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{
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struct mtk_serial_regs __iomem *regs =
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(void *) CONFIG_DEBUG_UART_BASE;
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while (!(readl(®s->lsr) & UART_LSR_THRE))
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;
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writel(ch, ®s->thr);
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}
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DEBUG_UART_FUNCS
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#endif |