mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-04 20:03:20 +09:00
d1259c9f5f
Add more information so that U-Boot can find the address of the serial port. Also fix the reg-shift value. Signed-off-by: Simon Glass <sjg@chromium.org>
70 lines
1.1 KiB
Plaintext
70 lines
1.1 KiB
Plaintext
/dts-v1/;
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/include/ "coreboot.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Google Link";
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compatible = "google,link", "intel,celeron-ivybridge";
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config {
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silent_console = <0>;
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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reg = <0 0x10>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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reg = <0x30 0x10>;
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bank-name = "B";
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};
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gpioc {
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compatible = "intel,ich6-gpio";
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reg = <0x40 0x10>;
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bank-name = "C";
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};
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serial {
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reg = <0x3f8 8>;
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clock-frequency = <115200>;
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};
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chosen { };
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memory { device_type = "memory"; reg = <0 0>; };
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich9";
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spi-flash@0 {
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reg = <0>;
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compatible = "winbond,w25q64", "spi-flash";
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memory-map = <0xff800000 0x00800000>;
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};
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};
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lpc {
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compatible = "intel,lpc";
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#address-cells = <1>;
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#size-cells = <1>;
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cros-ec@200 {
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compatible = "google,cros-ec";
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reg = <0x204 1 0x200 1 0x880 0x80>;
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/* This describes the flash memory within the EC */
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#address-cells = <1>;
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#size-cells = <1>;
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flash@8000000 {
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reg = <0x08000000 0x20000>;
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erase-value = <0xff>;
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};
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};
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};
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};
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