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https://github.com/brain-hackers/u-boot-brain
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![Thierry Reding](/assets/img/avatar_default.png)
size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com>
218 lines
4.1 KiB
C
218 lines
4.1 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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#include <linux/compiler.h>
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#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
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DECLARE_GLOBAL_DATA_PTR;
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__weak void arm_init_before_mmu(void)
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{
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}
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__weak void arm_init_domains(void)
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{
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}
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static void cp_delay (void)
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{
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volatile int i;
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/* copro seems to need some delay between reading and writing */
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for (i = 0; i < 100; i++)
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nop();
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asm volatile("" : : : "memory");
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}
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void set_section_dcache(int section, enum dcache_option option)
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{
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u32 *page_table = (u32 *)gd->arch.tlb_addr;
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u32 value;
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value = (section << MMU_SECTION_SHIFT) | (3 << 10);
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value |= option;
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page_table[section] = value;
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}
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__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
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{
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debug("%s: Warning: not implemented\n", __func__);
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}
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void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
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enum dcache_option option)
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{
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u32 *page_table = (u32 *)gd->arch.tlb_addr;
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unsigned long upto, end;
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end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
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start = start >> MMU_SECTION_SHIFT;
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debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
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option);
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for (upto = start; upto < end; upto++)
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set_section_dcache(upto, option);
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mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
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}
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__weak void dram_bank_mmu_setup(int bank)
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{
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bd_t *bd = gd->bd;
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int i;
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debug("%s: bank: %d\n", __func__, bank);
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for (i = bd->bi_dram[bank].start >> 20;
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i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
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i++) {
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#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
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set_section_dcache(i, DCACHE_WRITETHROUGH);
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#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
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set_section_dcache(i, DCACHE_WRITEALLOC);
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#else
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set_section_dcache(i, DCACHE_WRITEBACK);
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#endif
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}
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}
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/* to activate the MMU we need to set up virtual memory: use 1M areas */
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static inline void mmu_setup(void)
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{
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int i;
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u32 reg;
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arm_init_before_mmu();
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/* Set up an identity-mapping for all 4GB, rw for everyone */
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for (i = 0; i < 4096; i++)
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set_section_dcache(i, DCACHE_OFF);
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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dram_bank_mmu_setup(i);
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}
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/* Copy the page table address to cp15 */
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asm volatile("mcr p15, 0, %0, c2, c0, 0"
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: : "r" (gd->arch.tlb_addr) : "memory");
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/* Set the access control to all-supervisor */
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asm volatile("mcr p15, 0, %0, c3, c0, 0"
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: : "r" (~0));
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arm_init_domains();
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/* and enable the mmu */
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reg = get_cr(); /* get control reg. */
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cp_delay();
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set_cr(reg | CR_M);
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}
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static int mmu_enabled(void)
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{
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return get_cr() & CR_M;
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}
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/* cache_bit must be either CR_I or CR_C */
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static void cache_enable(uint32_t cache_bit)
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{
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uint32_t reg;
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/* The data cache is not active unless the mmu is enabled too */
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if ((cache_bit == CR_C) && !mmu_enabled())
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mmu_setup();
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reg = get_cr(); /* get control reg. */
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cp_delay();
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set_cr(reg | cache_bit);
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}
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/* cache_bit must be either CR_I or CR_C */
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static void cache_disable(uint32_t cache_bit)
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{
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uint32_t reg;
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reg = get_cr();
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cp_delay();
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if (cache_bit == CR_C) {
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/* if cache isn;t enabled no need to disable */
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if ((reg & CR_C) != CR_C)
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return;
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/* if disabling data cache, disable mmu too */
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cache_bit |= CR_M;
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}
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reg = get_cr();
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cp_delay();
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if (cache_bit == (CR_C | CR_M))
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flush_dcache_all();
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set_cr(reg & ~cache_bit);
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}
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#endif
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#ifdef CONFIG_SYS_ICACHE_OFF
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void icache_enable (void)
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{
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return;
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}
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void icache_disable (void)
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{
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return;
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}
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int icache_status (void)
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{
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return 0; /* always off */
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}
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#else
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void icache_enable(void)
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{
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cache_enable(CR_I);
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}
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void icache_disable(void)
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{
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cache_disable(CR_I);
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}
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int icache_status(void)
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{
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return (get_cr() & CR_I) != 0;
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}
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#endif
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#ifdef CONFIG_SYS_DCACHE_OFF
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void dcache_enable (void)
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{
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return;
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}
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void dcache_disable (void)
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{
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return;
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}
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int dcache_status (void)
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{
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return 0; /* always off */
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}
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#else
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void dcache_enable(void)
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{
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cache_enable(CR_C);
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}
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void dcache_disable(void)
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{
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cache_disable(CR_C);
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}
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int dcache_status(void)
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{
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return (get_cr() & CR_C) != 0;
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}
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#endif
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