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39b32be18c
This patch makes the common 4xx ECC code really usable on 440GP style platforms. Since the IBM DDR controller used on 440GP/GX/EP/GR is not register compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT we need to make some processor dependant defines used later on by the driver. Signed-off-by: Stefan Roese <sr@denx.de>
70 lines
2.4 KiB
C
70 lines
2.4 KiB
C
/*
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* Copyright (c) 2008 Nuovation System Designs, LLC
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* Grant Erickson <gerickson@nuovations.com>
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*
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* Copyright (c) 2007 DENX Software Engineering, GmbH
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* Stefan Roese <sr@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will abe useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Description:
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* This file implements ECC initialization for PowerPC processors
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* using the SDRAM DDR2 controller, including the 405EX(r),
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* 440SP(E), 460EX and 460GT.
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*
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*/
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#ifndef _ECC_H_
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#define _ECC_H_
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#if !defined(CFG_ECC_PATTERN)
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#define CFG_ECC_PATTERN 0x00000000
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#endif /* !defined(CFG_ECC_PATTERN) */
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/*
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* Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
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* compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
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* we need to make some processor dependant defines used later on by the
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* driver.
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*/
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/* For 440GP/GX/EP/GR */
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
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#define SDRAM_ECC_CFG SDRAM_CFG0
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#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK
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#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN
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#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK
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#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK
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#define SDRAM_ECC_CFG_DMWD_32 SDRAM_CFG0_DMWD_32
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#endif
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/* For 405EX/440SP/SPe/460EX/GT */
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
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#define SDRAM_ECC_CFG SDRAM_MCOPT1
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#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK
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#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN
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#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK
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#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK
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#define SDRAM_ECC_CFG_DMWD_32 SDRAM_MCOPT1_DMWD_32
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#endif
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extern void ecc_init(unsigned long * const start, unsigned long size);
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#endif /* _ECC_H_ */
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