mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 05:13:21 +09:00
680 lines
16 KiB
ArmAsm
680 lines
16 KiB
ArmAsm
/*
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* armboot - Startup Code for ARM720 CPU-core
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*
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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#include <asm/hardware.h>
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/*
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*************************************************************************
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*
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* Jump vector table as in table 3.1 in [1]
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*
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*************************************************************************
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*/
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.globl _start
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_start: b reset
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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#ifdef CONFIG_LPC2292
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.word 0xB4405F76 /* 2's complement of the checksum of the vectors */
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#else
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ldr pc, _not_used
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#endif
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from RAM!
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* relocate armboot to ram
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* setup stack
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* jump to second stage
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*
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*************************************************************************
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*/
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.globl _TEXT_BASE
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE
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/*
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* These are defined in the board-specific linker script.
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* Subtracting _start from them lets the linker put their
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* relative position in the executable instead of leaving
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* them null.
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*/
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.globl _bss_start_ofs
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_bss_start_ofs:
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.word __bss_start - _start
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.globl _bss_end_ofs
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_bss_end_ofs:
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.word _end - _start
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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/*
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* the actual reset code
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*/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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#endif
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#ifdef CONFIG_LPC2292
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bl lowlevel_init
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#endif
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/* Set stackpointer in internal RAM to call board_init_f */
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call_board_init_f:
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ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
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bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
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ldr r0,=0x00000000
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bl board_init_f
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/*------------------------------------------------------------------------------*/
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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*/
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.globl relocate_code
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relocate_code:
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mov r4, r0 /* save addr_sp */
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mov r5, r1 /* save addr of gd */
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mov r6, r2 /* save addr of destination */
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/* Set up the stack */
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stack_setup:
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mov sp, r4
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adr r0, _start
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cmp r0, r6
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beq clear_bss /* skip relocation */
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mov r1, r6 /* r1 <- scratch for copy_loop */
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ldr r2, _TEXT_BASE
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ldr r3, _bss_start_ofs
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add r2, r0, r3 /* r2 <- source end address */
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copy_loop:
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ldmia r0!, {r9-r10} /* copy from source address [r0] */
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stmia r1!, {r9-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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blo copy_loop
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#ifndef CONFIG_PRELOADER
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/*
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* fix .rel.dyn relocations
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*/
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ldr r0, _TEXT_BASE /* r0 <- Text base */
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sub r9, r6, r0 /* r9 <- relocation offset */
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ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
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add r10, r10, r0 /* r10 <- sym table in FLASH */
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ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
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add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
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ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
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add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
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fixloop:
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ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
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add r0, r0, r9 /* r0 <- location to fix up in RAM */
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ldr r1, [r2, #4]
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and r7, r1, #0xff
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cmp r7, #23 /* relative fixup? */
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beq fixrel
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cmp r7, #2 /* absolute fixup? */
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beq fixabs
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/* ignore unknown type of fixup */
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b fixnext
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fixabs:
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/* absolute fix: set location to (offset) symbol value */
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mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
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add r1, r10, r1 /* r1 <- address of symbol in table */
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ldr r1, [r1, #4] /* r1 <- symbol value */
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add r1, r1, r9 /* r1 <- relocated sym addr */
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b fixnext
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fixrel:
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/* relative fix: increase location by offset */
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ldr r1, [r0]
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add r1, r1, r9
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fixnext:
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str r1, [r0]
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add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
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cmp r2, r3
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blo fixloop
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#endif
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clear_bss:
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#ifndef CONFIG_PRELOADER
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ldr r0, _bss_start_ofs
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ldr r1, _bss_end_ofs
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ldr r3, _TEXT_BASE /* Text base */
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mov r4, r6 /* reloc addr */
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add r0, r0, r4
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add r1, r1, r4
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mov r2, #0x00000000 /* clear */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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bne clbss_l
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bl coloured_LED_init
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bl red_LED_on
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#endif
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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ldr r0, _board_init_r_ofs
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adr r1, _start
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add lr, r0, r1
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add lr, lr, r9
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/* setup parameters for board_init_r */
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mov r0, r5 /* gd_t */
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mov r1, r6 /* dest_addr */
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/* jump to it ... */
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mov pc, lr
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_board_init_r_ofs:
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.word board_init_r - _start
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_rel_dyn_start_ofs:
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.word __rel_dyn_start - _start
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_rel_dyn_end_ofs:
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.word __rel_dyn_end - _start
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_dynsym_start_ofs:
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.word __dynsym_start - _start
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
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/* Interupt-Controller base addresses */
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INTMR1: .word 0x80000280 @ 32 bit size
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INTMR2: .word 0x80001280 @ 16 bit size
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INTMR3: .word 0x80002280 @ 8 bit size
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/* SYSCONs */
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SYSCON1: .word 0x80000100
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SYSCON2: .word 0x80001100
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SYSCON3: .word 0x80002200
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#define CLKCTL 0x6 /* mask */
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#define CLKCTL_18 0x0 /* 18.432 MHz */
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#define CLKCTL_36 0x2 /* 36.864 MHz */
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#define CLKCTL_49 0x4 /* 49.152 MHz */
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#define CLKCTL_73 0x6 /* 73.728 MHz */
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#elif defined(CONFIG_LPC2292)
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PLLCFG_ADR: .word PLLCFG
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PLLFEED_ADR: .word PLLFEED
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PLLCON_ADR: .word PLLCON
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PLLSTAT_ADR: .word PLLSTAT
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VPBDIV_ADR: .word VPBDIV
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MEMMAP_ADR: .word MEMMAP
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#endif
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cpu_init_crit:
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#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
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/*
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* mask all IRQs by clearing all bits in the INTMRs
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*/
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mov r1, #0x00
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ldr r0, INTMR1
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str r1, [r0]
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ldr r0, INTMR2
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str r1, [r0]
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ldr r0, INTMR3
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str r1, [r0]
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15,0,r0,c1,c0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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mcr p15,0,r0,c1,c0
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#elif defined(CONFIG_NETARM)
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/*
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* prior to software reset : need to set pin PORTC4 to be *HRESET
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*/
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ldr r0, =NETARM_GEN_MODULE_BASE
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ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
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NETARM_GEN_PORT_DIR(0x10))
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str r1, [r0, #+NETARM_GEN_PORTC]
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/*
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* software reset : see HW Ref. Guide 8.2.4 : Software Service register
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* for an explanation of this process
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*/
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ldr r0, =NETARM_GEN_MODULE_BASE
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ldr r1, =NETARM_GEN_SW_SVC_RESETA
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str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
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ldr r1, =NETARM_GEN_SW_SVC_RESETB
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str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
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ldr r1, =NETARM_GEN_SW_SVC_RESETA
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str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
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ldr r1, =NETARM_GEN_SW_SVC_RESETB
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str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
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/*
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* setup PLL and System Config
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*/
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ldr r0, =NETARM_GEN_MODULE_BASE
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ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
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NETARM_GEN_SYS_CFG_BUSFULL | \
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NETARM_GEN_SYS_CFG_USER_EN | \
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NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
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NETARM_GEN_SYS_CFG_BUSARB_INT | \
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NETARM_GEN_SYS_CFG_BUSMON_EN )
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str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
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#ifndef CONFIG_NETARM_PLL_BYPASS
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ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
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NETARM_GEN_PLL_CTL_POLTST_DEF | \
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NETARM_GEN_PLL_CTL_INDIV(1) | \
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NETARM_GEN_PLL_CTL_ICP_DEF | \
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NETARM_GEN_PLL_CTL_OUTDIV(2) )
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str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
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#endif
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/*
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* mask all IRQs by clearing all bits in the INTMRs
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*/
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mov r1, #0
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ldr r0, =NETARM_GEN_MODULE_BASE
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str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
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#elif defined(CONFIG_S3C4510B)
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/*
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* Mask off all IRQ sources
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*/
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ldr r1, =REG_INTMASK
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ldr r0, =0x3FFFFF
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str r0, [r1]
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/*
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* Disable Cache
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*/
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ldr r0, =REG_SYSCFG
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ldr r1, =0x83ffffa0 /* cache-disabled */
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str r1, [r0]
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* No specific initialisation for IntegratorAP/CM720T as yet */
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#elif defined(CONFIG_LPC2292)
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/* Set-up PLL */
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mov r3, #0xAA
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mov r4, #0x55
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/* First disconnect and disable the PLL */
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ldr r0, PLLCON_ADR
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mov r1, #0x00
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str r1, [r0]
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ldr r0, PLLFEED_ADR /* start feed sequence */
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str r3, [r0]
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str r4, [r0] /* feed sequence done */
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/* Set new M and P values */
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ldr r0, PLLCFG_ADR
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mov r1, #0x23 /* M=4 and P=2 */
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str r1, [r0]
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ldr r0, PLLFEED_ADR /* start feed sequence */
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str r3, [r0]
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str r4, [r0] /* feed sequence done */
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/* Then enable the PLL */
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ldr r0, PLLCON_ADR
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mov r1, #0x01 /* PLL enable bit */
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str r1, [r0]
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ldr r0, PLLFEED_ADR /* start feed sequence */
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str r3, [r0]
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str r4, [r0] /* feed sequence done */
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/* Wait for the lock */
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ldr r0, PLLSTAT_ADR
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mov r1, #0x400 /* lock bit */
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lock_loop:
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ldr r2, [r0]
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and r2, r1, r2
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cmp r2, #0
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beq lock_loop
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/* And finally connect the PLL */
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ldr r0, PLLCON_ADR
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mov r1, #0x03 /* PLL enable bit and connect bit */
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str r1, [r0]
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ldr r0, PLLFEED_ADR /* start feed sequence */
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str r3, [r0]
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str r4, [r0] /* feed sequence done */
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/* Set-up VPBDIV register */
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ldr r0, VPBDIV_ADR
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mov r1, #0x01 /* VPB clock is same as process clock */
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str r1, [r0]
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#else
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#error No cpu_init_crit() defined for current CPU type
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#endif
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#ifdef CONFIG_ARM7_REVD
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/* set clock speed */
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/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
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/* !!! not doing DRAM refresh properly! */
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ldr r0, SYSCON3
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ldr r1, [r0]
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bic r1, r1, #CLKCTL
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orr r1, r1, #CLKCTL_36
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str r1, [r0]
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#endif
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#ifndef CONFIG_LPC2292
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mov ip, lr
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependent, you will
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* find a lowlevel_init.S in your board directory.
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*/
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bl lowlevel_init
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mov lr, ip
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#endif
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mov pc, lr
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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#define I_BIT 0x80
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/*
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* use bad_save_user_regs for abort/prefetch/undef/swi ...
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
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*/
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC
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ldr r2, IRQ_STACK_START_IN
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ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
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add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
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mov r0, sp
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.endm
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC
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stmdb r8, {sp, lr}^ @ Calling SP, LR
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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mov r0, sp
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.endm
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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subs pc, lr, #4 @ return & move spsr_svc into cpsr
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.endm
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.macro get_bad_stack
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ldr r13, IRQ_STACK_START_IN @ setup our mode stack
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str lr, [r13] @ save caller lr / spsr
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mrs lr, spsr
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str lr, [r13, #4]
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mov r13, #MODE_SVC @ prepare SVC-Mode
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msr spsr_c, r13
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mov lr, pc
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movs pc, lr
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.endm
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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/*
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* exception handlers
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*/
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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#ifdef CONFIG_USE_IRQ
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.align 5
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irq:
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get_irq_stack
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irq_save_user_regs
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bl do_irq
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irq_restore_user_regs
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.align 5
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fiq:
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get_fiq_stack
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/* someone ought to write a more effiction fiq_save_user_regs */
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irq_save_user_regs
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bl do_fiq
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irq_restore_user_regs
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#else
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.align 5
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irq:
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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#endif
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#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
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.align 5
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.globl reset_cpu
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reset_cpu:
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
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mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
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mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x2100 @ ..v....s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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#elif defined(CONFIG_NETARM)
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.align 5
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.globl reset_cpu
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reset_cpu:
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ldr r1, =NETARM_MEM_MODULE_BASE
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ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
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ldr r1, =0xFFFFF000
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and r0, r1, r0
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ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE)
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add r0, r1, r0
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ldr r4, =NETARM_GEN_MODULE_BASE
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ldr r1, =NETARM_GEN_SW_SVC_RESETA
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str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
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ldr r1, =NETARM_GEN_SW_SVC_RESETB
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str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
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ldr r1, =NETARM_GEN_SW_SVC_RESETA
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str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
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ldr r1, =NETARM_GEN_SW_SVC_RESETB
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str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
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mov pc, r0
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#elif defined(CONFIG_S3C4510B)
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/* Nothing done here as reseting the CPU is board specific, depending
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* on external peripherals such as watchdog timers, etc. */
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* No specific reset actions for IntegratorAP/CM720T as yet */
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#elif defined(CONFIG_LPC2292)
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.align 5
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.globl reset_cpu
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reset_cpu:
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mov pc, r0
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#else
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#error No reset_cpu() defined for current CPU type
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#endif
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