mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 02:49:44 +09:00
caa4daa2ae
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
126 lines
2.8 KiB
C
126 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <net.h>
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#include <asm/io.h>
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#include <netdev.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <asm/types.h>
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#include <fsl_dtsec.h>
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#include <asm/arch/soc.h>
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#include <asm/arch-fsl-layerscape/config.h>
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#include <asm/arch-fsl-layerscape/immap_lsch2.h>
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#include <asm/arch/fsl_serdes.h>
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#include <linux/delay.h>
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#include <net/pfe_eth/pfe_eth.h>
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#include <dm/platform_data/pfe_dm_eth.h>
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#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
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#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
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#define MASK_ETH_PHY_RST 0x00000100
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static inline void ls1012afrdm_reset_phy(void)
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{
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unsigned int val;
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struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
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setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
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val = in_be32(&pgpio->gpdat);
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setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
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mdelay(10);
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val = in_be32(&pgpio->gpdat);
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setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
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mdelay(50);
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}
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int pfe_eth_board_init(struct udevice *dev)
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{
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static int init_done;
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struct mii_dev *bus;
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struct pfe_mdio_info mac_mdio_info;
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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if (!init_done) {
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ls1012afrdm_reset_phy();
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mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
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mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
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bus = pfe_mdio_init(&mac_mdio_info);
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if (!bus) {
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printf("Failed to register mdio\n");
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return -1;
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}
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init_done = 1;
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}
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if (priv->gemac_port) {
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mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
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mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
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bus = pfe_mdio_init(&mac_mdio_info);
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if (!bus) {
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printf("Failed to register mdio\n");
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return -1;
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}
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}
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pfe_set_mdio(priv->gemac_port,
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miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
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if (!priv->gemac_port)
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/* MAC1 */
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC1_PHY_ADDR,
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PHY_INTERFACE_MODE_SGMII);
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else
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/* MAC2 */
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC2_PHY_ADDR,
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PHY_INTERFACE_MODE_SGMII);
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return 0;
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}
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static struct pfe_eth_pdata pfe_pdata0 = {
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.pfe_eth_pdata_mac = {
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.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
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.phy_interface = 0,
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},
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.pfe_ddr_addr = {
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.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
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.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
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},
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};
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static struct pfe_eth_pdata pfe_pdata1 = {
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.pfe_eth_pdata_mac = {
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.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
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.phy_interface = 1,
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},
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.pfe_ddr_addr = {
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.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
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.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
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},
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};
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U_BOOT_DEVICE(ls1012a_pfe0) = {
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.name = "pfe_eth",
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.plat = &pfe_pdata0,
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};
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U_BOOT_DEVICE(ls1012a_pfe1) = {
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.name = "pfe_eth",
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.plat = &pfe_pdata1,
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};
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