574 lines
14 KiB
Plaintext
574 lines
14 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP lx2160a SOC common device tree source
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*
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* Copyright 2018-2020 NXP
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "fsl,lx2160a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x80000000>;
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/* DRAM space - 1, size : 2 GB DRAM */
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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clockgen: clocking@1300000 {
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compatible = "fsl,ls2080a-clockgen";
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reg = <0 0x1300000 0 0xa0000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06200000 0 0x100000>; /* GICR */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <1 9 0x4>;
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};
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gic_lpi_base: syscon@0x80000000 {
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compatible = "gic-lpi-base";
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reg = <0x0 0x80000000 0x0 0x200000>;
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max-gic-redistributors = <16>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
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<1 14 0x8>, /* Physical NS PPI, active-low */
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<1 11 0x8>, /* Virtual PPI, active-low */
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<1 10 0x8>; /* Hypervisor PPI, active-low */
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};
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fspi: flexspi@20c0000 {
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compatible = "nxp,lx2160a-fspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20c0000 0x0 0x10000>,
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<0x0 0x20000000 0x0 0x10000000>;
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reg-names = "fspi_base", "fspi_mmap";
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "fspi_en", "fspi";
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c0: i2c@2000000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts = <0 34 4>;
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scl-gpio = <&gpio2 15 0>;
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status = "disabled";
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};
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i2c1: i2c@2010000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2010000 0x0 0x10000>;
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interrupts = <0 34 4>;
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status = "disabled";
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};
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i2c2: i2c@2020000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2020000 0x0 0x10000>;
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interrupts = <0 35 4>;
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status = "disabled";
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};
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i2c3: i2c@2030000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2030000 0x0 0x10000>;
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interrupts = <0 35 4>;
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status = "disabled";
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};
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i2c4: i2c@2040000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2040000 0x0 0x10000>;
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interrupts = <0 74 4>;
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scl-gpio = <&gpio2 16 0>;
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status = "disabled";
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};
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i2c5: i2c@2050000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2050000 0x0 0x10000>;
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interrupts = <0 74 4>;
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status = "disabled";
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};
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i2c6: i2c@2060000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2060000 0x0 0x10000>;
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interrupts = <0 75 4>;
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status = "disabled";
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};
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i2c7: i2c@2070000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2070000 0x0 0x10000>;
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interrupts = <0 75 4>;
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status = "disabled";
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};
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uart0: serial@21c0000 {
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compatible = "arm,pl011";
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reg = <0x0 0x21c0000 0x0 0x1000>;
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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uart1: serial@21d0000 {
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compatible = "arm,pl011";
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reg = <0x0 0x21d0000 0x0 0x1000>;
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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uart2: serial@21e0000 {
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compatible = "arm,pl011";
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reg = <0x0 0x21e0000 0x0 0x1000>;
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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uart3: serial@21f0000 {
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compatible = "arm,pl011";
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reg = <0x0 0x21f0000 0x0 0x1000>;
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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dspi0: dspi@2100000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <0 26 0x4>; /* Level high type */
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num-cs = <6>;
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};
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dspi1: dspi@2110000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <0 26 0x4>; /* Level high type */
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num-cs = <6>;
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};
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dspi2: dspi@2120000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2120000 0x0 0x10000>;
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interrupts = <0 241 0x4>; /* Level high type */
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num-cs = <6>;
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};
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gpio0: gpio@2300000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <0 36 4>;
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gpio-controller;
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little-endian;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2310000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2310000 0x0 0x10000>;
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interrupts = <0 36 4>;
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gpio-controller;
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little-endian;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@2320000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2320000 0x0 0x10000>;
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interrupts = <0 37 4>;
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gpio-controller;
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little-endian;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@2330000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2330000 0x0 0x10000>;
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interrupts = <0 37 4>;
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gpio-controller;
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little-endian;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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watchdog@23a0000 {
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compatible = "arm,sbsa-gwdt";
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reg = <0x0 0x23a0000 0 0x1000>,
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<0x0 0x2390000 0 0x1000>;
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timeout-sec = <30>;
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};
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usb0: usb3@3100000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3100000 0x0 0x10000>;
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interrupts = <0 80 0x4>; /* Level high type */
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dr_mode = "host";
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};
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usb1: usb3@3110000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3110000 0x0 0x10000>;
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interrupts = <0 81 0x4>; /* Level high type */
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dr_mode = "host";
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};
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esdhc0: esdhc@2140000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2140000 0x0 0x10000>;
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interrupts = <0 28 0x4>; /* Level high type */
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clocks = <&clockgen 4 1>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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little-endian;
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bus-width = <4>;
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status = "disabled";
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};
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esdhc1: esdhc@2150000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2150000 0x0 0x10000>;
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interrupts = <0 63 0x4>; /* Level high type */
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clocks = <&clockgen 4 1>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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non-removable;
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little-endian;
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bus-width = <4>;
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status = "disabled";
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};
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sata0: sata@3200000 {
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compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000>;
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interrupts = <0 133 4>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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sata1: sata@3210000 {
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compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3210000 0x0 0x10000>;
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interrupts = <0 136 4>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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sata2: sata@3220000 {
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compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3220000 0x0 0x10000>;
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interrupts = <0 97 4>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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sata3: sata@3230000 {
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compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3230000 0x0 0x10000>;
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interrupts = <0 100 4>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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pcie1: pcie@3400000 {
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compatible = "fsl,lx2160a-pcie";
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reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
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0x00 0x03480000 0x0 0x40000 /* LUT registers */
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0x00 0x034c0000 0x0 0x40000 /* PF control registers */
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0x80 0x00000000 0x0 0x2000>; /* configuration space */
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reg-names = "ccsr", "lut", "pf_ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie2: pcie@3500000 {
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compatible = "fsl,lx2160a-pcie";
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reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
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0x00 0x03580000 0x0 0x40000 /* LUT registers */
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0x00 0x035c0000 0x0 0x40000 /* PF control registers */
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0x88 0x00000000 0x0 0x2000>; /* configuration space */
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reg-names = "ccsr", "lut", "pf_ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <2>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie3: pcie@3600000 {
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compatible = "fsl,lx2160a-pcie";
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reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
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0x00 0x03680000 0x0 0x40000 /* LUT registers */
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0x00 0x036c0000 0x0 0x40000 /* PF control registers */
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0x90 0x00000000 0x0 0x2000>; /* configuration space */
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reg-names = "ccsr", "lut", "pf_ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie4: pcie@3700000 {
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compatible = "fsl,lx2160a-pcie";
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reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
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0x00 0x03780000 0x0 0x40000 /* LUT registers */
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0x00 0x037c0000 0x0 0x40000 /* PF control registers */
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0x98 0x00000000 0x0 0x2000>; /* configuration space */
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reg-names = "ccsr", "lut", "pf_ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie5: pcie@3800000 {
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compatible = "fsl,lx2160a-pcie";
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reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
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0x00 0x03880000 0x0 0x40000 /* LUT registers */
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0x00 0x038c0000 0x0 0x40000 /* PF control registers */
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0xa0 0x00000000 0x0 0x2000>; /* configuration space */
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reg-names = "ccsr", "lut", "pf_ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie6: pcie@3900000 {
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compatible = "fsl,lx2160a-pcie";
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reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
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0x00 0x03980000 0x0 0x40000 /* LUT registers */
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0x00 0x039c0000 0x0 0x40000 /* PF control registers */
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0xa8 0x00000000 0x0 0x2000>; /* configuration space */
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reg-names = "ccsr", "lut", "pf_ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc", "simple-mfd";
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reg = <0x00000008 0x0c000000 0 0x40>,
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<0x00000000 0x08340000 0 0x40000>;
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#address-cells = <3>;
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#size-cells = <1>;
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/*
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* Region type 0x0 - MC portals
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* Region type 0x1 - QBMAN portals
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*/
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ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
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0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
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dpmacs {
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compatible = "simple-mfd";
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#address-cells = <1>;
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#size-cells = <0>;
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dpmac1: dpmac@1 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x1>;
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status = "disabled";
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};
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dpmac2: dpmac@2 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x2>;
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status = "disabled";
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};
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dpmac3: dpmac@3 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x3>;
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status = "disabled";
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};
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dpmac4: dpmac@4 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x4>;
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status = "disabled";
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};
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dpmac5: dpmac@5 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x5>;
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status = "disabled";
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};
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dpmac6: dpmac@6 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x6>;
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status = "disabled";
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};
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dpmac7: dpmac@7 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x7>;
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status = "disabled";
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};
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dpmac8: dpmac@8 {
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compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac9: dpmac@9 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x9>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac10: dpmac@a {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xa>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac11: dpmac@b {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xb>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac12: dpmac@c {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xc>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac13: dpmac@d {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xd>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac14: dpmac@e {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xe>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac15: dpmac@f {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac16: dpmac@10 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac17: dpmac@11 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x11>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac18: dpmac@12 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
/* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
|
|
emdio1: mdio@8b96000 {
|
|
compatible = "fsl,ls-mdio";
|
|
reg = <0x0 0x8b96000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
|
|
emdio2: mdio@8b97000 {
|
|
compatible = "fsl,ls-mdio";
|
|
reg = <0x0 0x8b97000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
firmware {
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
};
|
|
};
|