York Sun 4baa38c51a driver/ddr/fsl: Revise workaround A008511 for A009803 ... DDR controller 5.2.1 has this erratum A008511 partially fixed. The workaround needs to be adjusted to take advantage of Vref training. This patch enables the training and force output enable to be off. Erratum A009803 requires the controller to be idel before enabling address parity. It was combined with workaround for A008511. With new A008511 flow, this flow needs to be changed to enabling data init (D_INIT) after the address parity is enabled. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>		2016-09-14 14:05:38 -07:00
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altera	ddr: altera: Repair DQ window centering code	2016-04-20 11:28:45 +02:00
fsl	driver/ddr/fsl: Revise workaround A008511 for A009803	2016-09-14 14:05:38 -07:00
marvell	arm: mvebu: a38x: Weed out floating point use	2016-05-20 11:01:00 +02:00
microchip	drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.	2016-02-01 22:14:01 +01:00