mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-04 18:40:42 +09:00
71c4ae3f6d
Rather than load the FPGA file from the FAT partition, look at entry in system EEPROM to decide which file to retrieve directly from the EXT3 partition. Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
301 lines
8.8 KiB
C
301 lines
8.8 KiB
C
/*
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* MATRIX VISION GmbH mvBlueLYNX-X
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*
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* Derived from omap3_beagle.h:
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* (C) Copyright 2006-2008
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* Configuration settings for the TI OMAP3530 Beagle board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP34XX 1 /* which is a 34XX */
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#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
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#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
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#define CONFIG_OMAP_GPIO
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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/*
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* Display CPU and Board information
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*/
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_MISC_INIT_R
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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#define CONFIG_SERIAL_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
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/* Sector */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
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#define CONFIG_SERIAL1 1 /* UART1 */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_GENERIC_MMC 1
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#define CONFIG_MMC 1
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#define CONFIG_OMAP_HSMMC 1
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#define CONFIG_DOS_PARTITION 1
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/* silent console by default */
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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#define CONFIG_SILENT_CONSOLE 1
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/* USB */
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#define CONFIG_MUSB_UDC 1
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#define CONFIG_USB_OMAP3 1
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#define CONFIG_TWL4030_USB 1
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/* USB device configuration */
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#define CONFIG_USB_DEVICE 1
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#define CONFIG_USB_TTY 1
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
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#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
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#define CONFIG_USBD_VENDORID 0x164c
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#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
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#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
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#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
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#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
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/* no FLASH available */
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#define CONFIG_SYS_NO_FLASH
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/* commands to include */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_IMLS /* List all found images */
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#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
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#define CONFIG_CMD_NFS /* NFS support */
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_FPGA
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0
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#define CONFIG_DRIVER_OMAP34XX_I2C 1
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#define CONFIG_I2C_MULTI_BUS 1
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/*
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* TWL4030
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*/
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#define CONFIG_TWL4030_POWER 1
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/* Environment information */
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#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
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#define CONFIG_BOOTDELAY 0
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_STOP_STR "S"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"silent=true\0" \
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"loadaddr=0x82000000\0" \
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"usbtty=cdc_acm\0" \
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"console=ttyO0,115200n8\0" \
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"mpurate=600\0" \
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"vram=12M\0" \
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"dvimode=1024x768-24@60\0" \
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"defaultdisplay=dvi\0" \
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"loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\
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"/lib/firmware/mvblx/${fpgafilename}; then " \
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"fpga load 0 ${loadaddr} ${filesize}; " \
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"fi;\0" \
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"mmcdev=0\0" \
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"mmcroot=/dev/mmcblk0p2 rw\0" \
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"mmcrootfstype=ext3 rootwait\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"mpurate=${mpurate} " \
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapfb.debug=y " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype} " \
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"${cmdline_suffix}\0" \
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"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
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"importbootenv=echo Importing environment from mmc ...; " \
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"env import -t $loadaddr $filesize\0" \
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"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"mmcbootcmd= " \
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"echo Trying mmc${mmcdev}; " \
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"mmc dev ${mmcdev}; " \
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"if mmc rescan; then " \
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"setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
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"echo SD/MMC found on device ${mmcdev};" \
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"if run loadbootenv; then " \
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"echo Loading boot environment from mmc${mmcdev}; " \
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"run importbootenv; " \
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"fi;" \
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"run loadfpga; " \
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"if test -n $uenvcmd; then " \
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"echo Running uenvcmd ...;" \
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"run uenvcmd;" \
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"fi;" \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"fi;" \
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"fi\0"
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#define CONFIG_BOOTCOMMAND \
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"setenv mmcdev 1;" \
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"run mmcbootcmd || " \
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"setenv mmcdev 0;" \
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"run mmcbootcmd"
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#define CONFIG_AUTO_COMPLETE 1
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT "mvblx # "
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
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#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
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#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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#define CONFIG_ENV_IS_NOWHERE 1
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/*----------------------------------------------------------------------------
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* Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
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*----------------------------------------------------------------------------
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*/
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_SMC911X 1
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#define CONFIG_SMC911X_32_BIT
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#define CONFIG_SMC911X_BASE 0x2C000000
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#endif /* (CONFIG_CMD_NET) */
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#define CONFIG_FPGA_COUNT 1
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#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
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#define CONFIG_FPGA_ALTERA
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#define CONFIG_FPGA_CYCLON2
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#define CONFIG_SYS_FPGA_PROG_FEEDBACK
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#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_EEPROM_BUS_NUM 2
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_OMAP3_SPI
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#endif /* __CONFIG_H */
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