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https://github.com/brain-hackers/u-boot-brain
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95b602bab5
The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
127 lines
4.1 KiB
C
127 lines
4.1 KiB
C
#include <common.h>
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#include <asm/u-boot.h>
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#include <asm/processor.h>
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#include "exbitgen.h"
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void sdram_init(void);
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/* ************************************************************************ */
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int board_early_init_f (void)
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/* ------------------------------------------------------------------------ --
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* Purpose :
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* Remarks :
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* Restrictions:
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* See also :
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* Example :
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* ************************************************************************ */
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{
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unsigned long i;
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the Walnut board.
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| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
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| IRQ 16 405GP internally generated; active low; level sensitive
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| IRQ 17-24 RESERVED
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| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
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| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
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| IRQ 27 (EXT IRQ 2) Not Used
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| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
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| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
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| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
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| Note for Walnut board:
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| An interrupt taken for the FPGA (IRQ 25) indicates that either
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| the Mouse, Keyboard, IRDA, or External Expansion caused the
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| interrupt. The FPGA must be read to determine which device
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| caused the interrupt. The default setting of the FPGA clears
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+-------------------------------------------------------------------------*/
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */
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mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
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mtdcr (UIC0PR, 0xFFFFFF90); /* set int polarities */
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/* Perform reset of PHY connected to PPC via register in CPLD */
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out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */
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for (i = 0; i < 10000000; i++) {
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;
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}
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out8 (PHY_CTRL_ADDR, 0x2f); /* deactivate nRESET */
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return 0;
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}
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/* ************************************************************************ */
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int checkboard (void)
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/* ------------------------------------------------------------------------ --
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* Purpose :
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* Remarks :
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* Restrictions:
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* See also :
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* Example :
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* ************************************************************************ */
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{
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printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR));
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return (0);
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}
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/* ************************************************************************ */
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phys_size_t initdram (int board_type)
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/* ------------------------------------------------------------------------ --
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* Purpose : Determines size of mounted DRAM.
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* Remarks : Size is determined by reading SDRAM configuration registers as
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* set up by sdram_init.
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* Restrictions:
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* See also :
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* Example :
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* ************************************************************************ */
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{
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ulong tot_size;
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ulong bank_size;
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ulong tmp;
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/*
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* ToDo: Move the asm init routine sdram_init() to this C file,
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* or even better use some common ppc4xx code available
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* in cpu/ppc4xx
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*/
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sdram_init();
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tot_size = 0;
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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return tot_size;
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}
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